Home
last modified time | relevance | path

Searched refs:NUM_CHANNELS (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h17 #define NUM_CHANNELS 1 /* number of channels */ macro
76 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
80 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
81 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
82 uint32_t wcmd[NUM_CHANNELS];
144 uint32_t channel_size[NUM_CHANNELS];
145 uint32_t column_bits[NUM_CHANNELS];
[all …]
/OK3568_Linux_fs/u-boot/drivers/pwm/
H A Dsandbox_pwm.c17 NUM_CHANNELS = 3, enumerator
28 struct sandbox_pwm_chan chan[NUM_CHANNELS];
37 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_config()
52 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_enable()
66 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_invert()
/OK3568_Linux_fs/kernel/drivers/staging/rtl8712/
H A Drtl871x_rf.h26 #define NUM_CHANNELS 15 macro
30 u8 channel_set[NUM_CHANNELS];
31 u8 channel_cck_power[NUM_CHANNELS]; /*dbm*/
32 u8 channel_ofdm_power[NUM_CHANNELS];/*dbm*/
/OK3568_Linux_fs/kernel/drivers/staging/most/i2c/
H A Di2c.c18 enum { CH_RX, CH_TX, NUM_CHANNELS }; enumerator
36 struct most_channel_capability capabilities[NUM_CHANNELS];
71 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in configure_channel()
125 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in enqueue()
170 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in poison_channel()
300 for (i = 0; i < NUM_CHANNELS; i++) { in i2c_probe()
312 dev->most_iface.num_channels = NUM_CHANNELS; in i2c_probe()
/OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/
H A Dsmc.c285 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
309 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
940 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
976 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1012 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1064 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1362 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1390 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1417 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in rcvn_cal()
1451 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
[all …]
H A Dmrc_util.c1359 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()
1456 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
/OK3568_Linux_fs/buildroot/package/opentyrian/
H A D0001-Move-definitions-that-don-t-need-to-be-exposed-from-opl-h-to-opl-c.patch40 +#undef NUM_CHANNELS
42 +#define NUM_CHANNELS 18
44 +#define NUM_CHANNELS 9
47 +#define MAXOPERATORS (NUM_CHANNELS*2)
211 -#undef NUM_CHANNELS
213 -#define NUM_CHANNELS 18
215 -#define NUM_CHANNELS 9
218 -#define MAXOPERATORS (NUM_CHANNELS*2)
/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Dip22zilog.c54 #define NUM_CHANNELS (NUM_IP22ZILOG * 2) macro
963 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); in ip22zilog_alloc_tables()
1071 .nr = NUM_CHANNELS,
1087 for (channel = 0; channel < NUM_CHANNELS; channel++) in ip22zilog_prepare()
1090 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; in ip22zilog_prepare()
1092 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) in ip22zilog_prepare()
1134 for (channel = 0; channel < NUM_CHANNELS; channel++) { in ip22zilog_prepare()
1171 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_ports_init()
1195 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_exit()
/OK3568_Linux_fs/kernel/drivers/edac/
H A Dskx_common.h39 #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) macro
75 } chan[NUM_CHANNELS];
H A Dsb_edac.c286 #define NUM_CHANNELS 6 /* Max channels per MC */ macro
383 struct pci_dev *pci_tad[NUM_CHANNELS];
388 struct sbridge_channel channel[NUM_CHANNELS];
1586 : NUM_CHANNELS; in __populate_dimms()
1855 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()
1875 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()
2250 if (channel >= NUM_CHANNELS) { in get_memory_error_data_from_mce()
3073 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); in sbridge_mce_output_error()
3230 KNL_MAX_CHANNELS : NUM_CHANNELS; in sbridge_register_mci()
H A Dskx_common.c402 layers[0].size = NUM_CHANNELS; in skx_register_mci()
641 for (j = 0; j < NUM_CHANNELS; j++) { in skx_remove()
/OK3568_Linux_fs/kernel/drivers/net/wireless/intersil/orinoco/
H A Dcfg.c59 for (i = 0; i < NUM_CHANNELS; i++) { in orinoco_wiphy_register()
183 if ((channel < 1) || (channel > NUM_CHANNELS) || in orinoco_set_monitor_channel()
H A Dhw.h21 #define NUM_CHANNELS 14 macro
H A Dhw.c1189 if ((channel < 1) || (channel > NUM_CHANNELS)) { in orinoco_hw_get_freq()
H A Dwext.c450 if ((chan < 1) || (chan > NUM_CHANNELS) || in orinoco_ioctl_setfreq()
/OK3568_Linux_fs/kernel/drivers/clk/berlin/
H A Dberlin2-avpll.c29 #define NUM_CHANNELS 8 macro
/OK3568_Linux_fs/kernel/drivers/net/ethernet/toshiba/
H A Dps3_gelic_wireless.c52 #define NUM_CHANNELS ARRAY_SIZE(channel_freq) macro
315 i < NUM_CHANNELS && chs < IW_MAX_FREQUENCIES; i++) in gelic_wl_get_range()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Ddw-dp.c111 #define NUM_CHANNELS GENMASK(14, 12) macro
3708 AUDIO_DATA_IN_EN | NUM_CHANNELS | AUDIO_DATA_WIDTH | in dw_dp_audio_hw_params()
3711 FIELD_PREP(NUM_CHANNELS, num_channels) | in dw_dp_audio_hw_params()
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Ddw-dp.c97 #define NUM_CHANNELS GENMASK(14, 12) macro