1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2015 Google, Inc
3*4882a593Smuzhiyun * Written by Simon Glass <sjg@chromium.org>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <pwm.h>
12*4882a593Smuzhiyun #include <asm/test.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun enum {
17*4882a593Smuzhiyun NUM_CHANNELS = 3,
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct sandbox_pwm_chan {
21*4882a593Smuzhiyun uint period_ns;
22*4882a593Smuzhiyun uint duty_ns;
23*4882a593Smuzhiyun bool enable;
24*4882a593Smuzhiyun bool polarity;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct sandbox_pwm_priv {
28*4882a593Smuzhiyun struct sandbox_pwm_chan chan[NUM_CHANNELS];
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
sandbox_pwm_set_config(struct udevice * dev,uint channel,uint period_ns,uint duty_ns)31*4882a593Smuzhiyun static int sandbox_pwm_set_config(struct udevice *dev, uint channel,
32*4882a593Smuzhiyun uint period_ns, uint duty_ns)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct sandbox_pwm_priv *priv = dev_get_priv(dev);
35*4882a593Smuzhiyun struct sandbox_pwm_chan *chan;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (channel >= NUM_CHANNELS)
38*4882a593Smuzhiyun return -ENOSPC;
39*4882a593Smuzhiyun chan = &priv->chan[channel];
40*4882a593Smuzhiyun chan->period_ns = period_ns;
41*4882a593Smuzhiyun chan->duty_ns = duty_ns;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
sandbox_pwm_set_enable(struct udevice * dev,uint channel,bool enable)46*4882a593Smuzhiyun static int sandbox_pwm_set_enable(struct udevice *dev, uint channel,
47*4882a593Smuzhiyun bool enable)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct sandbox_pwm_priv *priv = dev_get_priv(dev);
50*4882a593Smuzhiyun struct sandbox_pwm_chan *chan;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (channel >= NUM_CHANNELS)
53*4882a593Smuzhiyun return -ENOSPC;
54*4882a593Smuzhiyun chan = &priv->chan[channel];
55*4882a593Smuzhiyun chan->enable = enable;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
sandbox_pwm_set_invert(struct udevice * dev,uint channel,bool polarity)60*4882a593Smuzhiyun static int sandbox_pwm_set_invert(struct udevice *dev, uint channel,
61*4882a593Smuzhiyun bool polarity)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct sandbox_pwm_priv *priv = dev_get_priv(dev);
64*4882a593Smuzhiyun struct sandbox_pwm_chan *chan;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (channel >= NUM_CHANNELS)
67*4882a593Smuzhiyun return -ENOSPC;
68*4882a593Smuzhiyun chan = &priv->chan[channel];
69*4882a593Smuzhiyun chan->polarity = polarity;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct pwm_ops sandbox_pwm_ops = {
75*4882a593Smuzhiyun .set_config = sandbox_pwm_set_config,
76*4882a593Smuzhiyun .set_enable = sandbox_pwm_set_enable,
77*4882a593Smuzhiyun .set_invert = sandbox_pwm_set_invert,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct udevice_id sandbox_pwm_ids[] = {
81*4882a593Smuzhiyun { .compatible = "sandbox,pwm" },
82*4882a593Smuzhiyun { }
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun U_BOOT_DRIVER(warm_pwm_sandbox) = {
86*4882a593Smuzhiyun .name = "pwm_sandbox",
87*4882a593Smuzhiyun .id = UCLASS_PWM,
88*4882a593Smuzhiyun .of_match = sandbox_pwm_ids,
89*4882a593Smuzhiyun .ops = &sandbox_pwm_ops,
90*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct sandbox_pwm_priv),
91*4882a593Smuzhiyun };
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