Searched refs:KS2_EDMA0_BASE (Results 1 – 2 of 2) sorted by relevance
180 edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot); in ddr3_reset_data()188 qedma3_start(KS2_EDMA0_BASE, &edma_channel); in ddr3_reset_data()219 edma3_set_src_addr(KS2_EDMA0_BASE, in ddr3_reset_data()221 edma3_set_dest_addr(KS2_EDMA0_BASE, in ddr3_reset_data()224 while (edma3_check_for_transfer(KS2_EDMA0_BASE, in ddr3_reset_data()230 qedma3_stop(KS2_EDMA0_BASE, &edma_channel); in ddr3_reset_data()
120 #define KS2_EDMA0_BASE 0x02700000 macro