Searched refs:CPU_ACLK_HZ (Results 1 – 4 of 4) sorted by relevance
413 aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); in rkclk_init()414 assert((aclk_div + 1) * CPU_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); in rkclk_init()422 hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); in rkclk_init()423 assert((1 << hclk_div) * CPU_HCLK_HZ <= CPU_ACLK_HZ && hclk_div < 0x3); in rkclk_init()424 pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); in rkclk_init()425 assert((1 << pclk_div) * CPU_PCLK_HZ <= CPU_ACLK_HZ && pclk_div < 0x4); in rkclk_init()
443 aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; in rkclk_init()444 assert((aclk_div + 1) * CPU_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()452 hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); in rkclk_init()453 assert((1 << hclk_div) * CPU_HCLK_HZ <= CPU_ACLK_HZ && hclk_div < 0x3); in rkclk_init()454 pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); in rkclk_init()455 assert((1 << pclk_div) * CPU_PCLK_HZ <= CPU_ACLK_HZ && pclk_div < 0x4); in rkclk_init()
17 #define CPU_ACLK_HZ 297000000 macro