Searched refs:CLK_PWM0_SEL_SHIFT (Results 1 – 8 of 8) sorted by relevance
275 CLK_PWM0_SEL_SHIFT = 0, enumerator276 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
200 CLK_PWM0_SEL_SHIFT = 6, enumerator201 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
187 CLK_PWM0_SEL_SHIFT = 7, enumerator188 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
154 CLK_PWM0_SEL_SHIFT = 7, enumerator155 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
629 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1106_pwm_get_clk()672 src_clk << CLK_PWM0_SEL_SHIFT); in rv1106_pwm_set_clk()
292 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rk3568_pwm_get_pmuclk()318 CLK_PWM0_SEL_SHIFT) | in rk3568_pwm_set_pmuclk()319 0 << CLK_PWM0_SEL_SHIFT); in rk3568_pwm_set_pmuclk()325 (CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) | in rk3568_pwm_set_pmuclk()
269 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1126_pwm_get_pmuclk()299 CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT); in rv1126_pwm_set_pmuclk()310 CLK_PWM0_SEL_GPLL << CLK_PWM0_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
785 shift = CLK_PWM0_SEL_SHIFT; in rk3528_pwm_get_clk()827 shift = CLK_PWM0_SEL_SHIFT; in rk3528_pwm_set_clk()