Searched refs:CLK_HCLK_ARM_PLL_DIV_4 (Results 1 – 2 of 2) sorted by relevance
123 case CLK_HCLK_ARM_PLL_DIV_4: in get_sdram_clk_rate()
81 #define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) macro