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Searched refs:BIT8 (Results 1 – 25 of 224) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/hal/phydm/rtl8188e/
H A Dphydm_rtl8188e.c219 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF in odm_DynamicPrimaryCCA()
246 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF in odm_DynamicPrimaryCCA()
283 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); in odm_DynamicPrimaryCCA()
332 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); in odm_DynamicPrimaryCCA()
334 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); in odm_DynamicPrimaryCCA()
348 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); in odm_DynamicPrimaryCCA()
350 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); in odm_DynamicPrimaryCCA()
448 ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0); in odm_DynamicPrimaryCCA()
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/include/
H A Dhal_com_reg.h665 #define RRSR_24M BIT8
845 #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
861 #define IMR_CPWM BIT8
893 #define PHIMR_CPWM BIT8
916 #define PHIMR_RXFOVW BIT8
944 #define UHIMR_CPWM BIT8
969 #define UHIMR_RXFOVW BIT8
998 #define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear
1027 #define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow
1092 #define RCR_ACRC32 BIT8 // Accept CRC32 error packet
H A Drtl8723b_spec.h244 #define IMR_CPWM_8723B BIT8 // CPU power Mode exchange INT Status, Write 1 clear
273 #define IMR_RXFOVW_8723B BIT8 // Receive FIFO Overflow
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/include/
H A Dhal_com_reg.h665 #define RRSR_24M BIT8
845 #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
861 #define IMR_CPWM BIT8
893 #define PHIMR_CPWM BIT8
916 #define PHIMR_RXFOVW BIT8
944 #define UHIMR_CPWM BIT8
969 #define UHIMR_RXFOVW BIT8
998 #define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear
1027 #define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow
1092 #define RCR_ACRC32 BIT8 // Accept CRC32 error packet
H A Drtl8812a_spec.h197 #define IMR_CPWM_8812 BIT8 // CPU power Mode exchange INT Status, Write 1 clear
226 #define IMR_RXFOVW_8812 BIT8 // Receive FIFO Overflow
H A Drtl8723b_spec.h244 #define IMR_CPWM_8723B BIT8 // CPU power Mode exchange INT Status, Write 1 clear
273 #define IMR_RXFOVW_8723B BIT8 // Receive FIFO Overflow
/OK3568_Linux_fs/kernel/drivers/staging/rtl8723bs/include/
H A Dhal_com_reg.h616 #define RRSR_24M BIT8
796 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */
812 #define IMR_CPWM BIT8
844 #define PHIMR_CPWM BIT8
867 #define PHIMR_RXFOVW BIT8
895 #define UHIMR_CPWM BIT8
920 #define UHIMR_RXFOVW BIT8
949 #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
978 #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */
1043 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
H A Drtl8723b_spec.h218 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
247 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/hal/phydm/
H A Dphydm_antdiv.c237 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX in ODM_UpdateRxIdleAnt()
254 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX in ODM_UpdateRxIdleAnt()
265 value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); in ODM_UpdateRxIdleAnt()
283 ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt); //PathA Resp Tx in ODM_UpdateRxIdleAnt()
827 …ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //an… in odm_RX_HWAntDiv_Init_88E()
865 …ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //an… in odm_TRX_HWAntDiv_Init_88E()
878 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 in odm_TRX_HWAntDiv_Init_88E()
935 …ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by… in odm_Smart_HWAntDiv_Init_88E()
946 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 in odm_Smart_HWAntDiv_Init_88E()
959 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 in odm_Smart_HWAntDiv_Init_88E()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/include/
H A Dhal_com_reg.h684 #define RRSR_24M BIT8
872 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */
888 #define IMR_CPWM BIT8
920 #define PHIMR_CPWM BIT8
943 #define PHIMR_RXFOVW BIT8
971 #define UHIMR_CPWM BIT8
996 #define UHIMR_RXFOVW BIT8
1025 #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
1054 #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */
1119 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
H A Drtl8723b_spec.h244 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
273 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/
H A Dphydm_antdiv.c267 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX in ODM_UpdateRxIdleAnt()
296 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ in ODM_UpdateRxIdleAnt()
307 value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); in ODM_UpdateRxIdleAnt()
326 ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, Default_tx_Ant); /*PathA Resp Tx*/ in ODM_UpdateRxIdleAnt()
872 …ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //an… in odm_RX_HWAntDiv_Init_88E()
909 …ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //an… in odm_TRX_HWAntDiv_Init_88E()
922 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 in odm_TRX_HWAntDiv_Init_88E()
979 …ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by… in odm_Smart_HWAntDiv_Init_88E()
990 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 in odm_Smart_HWAntDiv_Init_88E()
1003 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 in odm_Smart_HWAntDiv_Init_88E()
[all …]
H A Dphydm_pathdiv.c97 ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); in phydm_dtp_fix_tx_path()
107 ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); in phydm_dtp_fix_tx_path()
117 ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); in phydm_dtp_fix_tx_path()
166 ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); in phydm_dtp_fix_tx_path()
182 ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); in phydm_dtp_fix_tx_path()
199 ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); in phydm_dtp_fix_tx_path()
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/phydm/
H A Dphydm_antdiv.c220 ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX in ODM_UpdateRxIdleAnt()
246 ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ in ODM_UpdateRxIdleAnt()
257 value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); in ODM_UpdateRxIdleAnt()
275 ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt); //PathA Resp Tx in ODM_UpdateRxIdleAnt()
817 …ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //an… in odm_RX_HWAntDiv_Init_88E()
854 …ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //an… in odm_TRX_HWAntDiv_Init_88E()
867 ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 in odm_TRX_HWAntDiv_Init_88E()
924 …ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by… in odm_Smart_HWAntDiv_Init_88E()
935 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 in odm_Smart_HWAntDiv_Init_88E()
948 ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 in odm_Smart_HWAntDiv_Init_88E()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/txbf/
H A Dhaltxbf8822b.c554 pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); in HalTxbf8822B_Enter()
555 pBeamformingInfo->RegMUTxCtrl |= (pBeamformeeEntry->mu_reg_index << 8)&(BIT8|BIT9|BIT10); in HalTxbf8822B_Enter()
840 pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); in HalTxbf8822B_Status()
841 pBeamformingInfo->RegMUTxCtrl |= ((idx<<8)&(BIT8|BIT9|BIT10)); in HalTxbf8822B_Status()
884 pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); in HalTxbf8822B_ConfigGtab()
907 pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); in HalTxbf8822B_ConfigGtab()
908 pBeamformingInfo->RegMUTxCtrl |= BIT8; in HalTxbf8822B_ConfigGtab()
1081 ODM_SetBBReg(pDM_Odm, 0x19f0, BIT9|BIT8, Nr); in phydm_8822b_sutxbfer_workaroud()
1087 ODM_SetBBReg(pDM_Odm, 0xb58, BIT9|BIT8, BW); in phydm_8822b_sutxbfer_workaroud()
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/
H A Drtl8812a_spec.h204 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
233 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/
H A Drtl8812a_spec.h204 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
233 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/include/
H A Drtl8812a_spec.h205 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
234 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/include/
H A Drtl8812a_spec.h205 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
234 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/
H A Drtl8812a_spec.h205 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
234 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/include/
H A Drtl8812a_spec.h204 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
233 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/include/
H A Drtl8812a_spec.h205 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
234 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/include/
H A Drtl8812a_spec.h205 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
234 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/
H A Drtl8812a_spec.h204 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
233 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/
H A Drtl8812a_spec.h204 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
233 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */

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