1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8812A_SPEC_H__ 16*4882a593Smuzhiyun #define __RTL8812A_SPEC_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <drv_conf.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* ************************************************************ 22*4882a593Smuzhiyun * 8812 Regsiter offset definition 23*4882a593Smuzhiyun * ************************************************************ */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* ************************************************************ 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * ************************************************************ */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* ----------------------------------------------------- 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * 0x0000h ~ 0x00FFh System Configuration 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * ----------------------------------------------------- */ 34*4882a593Smuzhiyun #define REG_SYS_CLKR_8812A 0x0008 35*4882a593Smuzhiyun #define REG_AFE_PLL_CTRL_8812A 0x0028 36*4882a593Smuzhiyun #define REG_HSIMR_8812 0x0058 37*4882a593Smuzhiyun #define REG_HSISR_8812 0x005c 38*4882a593Smuzhiyun #define REG_GPIO_EXT_CTRL 0x0060 39*4882a593Smuzhiyun #define REG_GPIO_STATUS_8812 0x006C 40*4882a593Smuzhiyun #define REG_SDIO_CTRL_8812 0x0070 41*4882a593Smuzhiyun #define REG_OPT_CTRL_8812 0x0074 42*4882a593Smuzhiyun #define REG_RF_B_CTRL_8812 0x0076 43*4882a593Smuzhiyun #define REG_FW_DRV_MSG_8812 0x0088 44*4882a593Smuzhiyun #define REG_HMEBOX_E2_E3_8812 0x008C 45*4882a593Smuzhiyun #define REG_HIMR0_8812 0x00B0 46*4882a593Smuzhiyun #define REG_HISR0_8812 0x00B4 47*4882a593Smuzhiyun #define REG_HIMR1_8812 0x00B8 48*4882a593Smuzhiyun #define REG_HISR1_8812 0x00BC 49*4882a593Smuzhiyun #define REG_EFUSE_BURN_GNT_8812 0x00CF 50*4882a593Smuzhiyun #define REG_SYS_CFG1_8812 0x00FC 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* ----------------------------------------------------- 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * 0x0100h ~ 0x01FFh MACTOP General Configuration 55*4882a593Smuzhiyun * 56*4882a593Smuzhiyun * ----------------------------------------------------- */ 57*4882a593Smuzhiyun #define REG_CR_8812A 0x100 58*4882a593Smuzhiyun #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 59*4882a593Smuzhiyun #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 60*4882a593Smuzhiyun #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 61*4882a593Smuzhiyun #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define REG_RSVD3_8812 0x0168 64*4882a593Smuzhiyun #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 65*4882a593Smuzhiyun #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 66*4882a593Smuzhiyun #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define REG_HMEBOX_EXT0_8812 0x01F0 69*4882a593Smuzhiyun #define REG_HMEBOX_EXT1_8812 0x01F4 70*4882a593Smuzhiyun #define REG_HMEBOX_EXT2_8812 0x01F8 71*4882a593Smuzhiyun #define REG_HMEBOX_EXT3_8812 0x01FC 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* ----------------------------------------------------- 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * 0x0200h ~ 0x027Fh TXDMA Configuration 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * ----------------------------------------------------- */ 78*4882a593Smuzhiyun #define REG_DWBCN0_CTRL_8812 REG_TDECTRL 79*4882a593Smuzhiyun #define REG_DWBCN1_CTRL_8812 0x0228 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* ----------------------------------------------------- 82*4882a593Smuzhiyun * 83*4882a593Smuzhiyun * 0x0280h ~ 0x02FFh RXDMA Configuration 84*4882a593Smuzhiyun * 85*4882a593Smuzhiyun * ----------------------------------------------------- */ 86*4882a593Smuzhiyun #define REG_TDECTRL_8812A 0x0208 87*4882a593Smuzhiyun #define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/ 88*4882a593Smuzhiyun #define REG_RXDMA_PRO_8812 0x0290 89*4882a593Smuzhiyun #define REG_EARLY_MODE_CONTROL_8812 0x02BC 90*4882a593Smuzhiyun #define REG_RSVD5_8812 0x02F0 91*4882a593Smuzhiyun #define REG_RSVD6_8812 0x02F4 92*4882a593Smuzhiyun #define REG_RSVD7_8812 0x02F8 93*4882a593Smuzhiyun #define REG_RSVD8_8812 0x02FC 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* ----------------------------------------------------- 97*4882a593Smuzhiyun * 98*4882a593Smuzhiyun * 0x0300h ~ 0x03FFh PCIe 99*4882a593Smuzhiyun * 100*4882a593Smuzhiyun * ----------------------------------------------------- */ 101*4882a593Smuzhiyun #define REG_PCIE_CTRL_REG_8812A 0x0300 102*4882a593Smuzhiyun #define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */ 103*4882a593Smuzhiyun #define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */ 104*4882a593Smuzhiyun #define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ 105*4882a593Smuzhiyun #define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ 106*4882a593Smuzhiyun #define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */ 107*4882a593Smuzhiyun #define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */ 108*4882a593Smuzhiyun #define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ 109*4882a593Smuzhiyun #define REG_PCIE_HRPWM_8812A 0x0361 /* PCIe RPWM */ 110*4882a593Smuzhiyun #define REG_PCIE_HCPWM_8812A 0x0363 /* PCIe CPWM */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* ----------------------------------------------------- 115*4882a593Smuzhiyun * 116*4882a593Smuzhiyun * 0x0400h ~ 0x047Fh Protocol Configuration 117*4882a593Smuzhiyun * 118*4882a593Smuzhiyun * ----------------------------------------------------- */ 119*4882a593Smuzhiyun #define REG_TXPKT_EMPTY_8812A 0x041A 120*4882a593Smuzhiyun #define REG_FWHW_TXQ_CTRL_8812A 0x0420 121*4882a593Smuzhiyun #define REG_TXBF_CTRL_8812A 0x042C 122*4882a593Smuzhiyun #define REG_ARFR0_8812 0x0444 123*4882a593Smuzhiyun #define REG_ARFR1_8812 0x044C 124*4882a593Smuzhiyun #define REG_CCK_CHECK_8812 0x0454 125*4882a593Smuzhiyun #define REG_AMPDU_MAX_TIME_8812 0x0456 126*4882a593Smuzhiyun #define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define REG_AMPDU_MAX_LENGTH_8812 0x0458 129*4882a593Smuzhiyun #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D 130*4882a593Smuzhiyun #define REG_NDPA_OPT_CTRL_8812A 0x045F 131*4882a593Smuzhiyun #define REG_DATA_SC_8812 0x0483 132*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 133*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_LOW 0x0484 134*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_HIGH 0x0488 135*4882a593Smuzhiyun #endif 136*4882a593Smuzhiyun #define REG_ARFR2_8812 0x048C 137*4882a593Smuzhiyun #define REG_ARFR3_8812 0x0494 138*4882a593Smuzhiyun #define REG_TXRPT_START_OFFSET 0x04AC 139*4882a593Smuzhiyun #define REG_AMPDU_BURST_MODE_8812 0x04BC 140*4882a593Smuzhiyun #define REG_HT_SINGLE_AMPDU_8812 0x04C7 141*4882a593Smuzhiyun #define REG_MACID_PKT_DROP0_8812 0x04D0 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* ----------------------------------------------------- 144*4882a593Smuzhiyun * 145*4882a593Smuzhiyun * 0x0500h ~ 0x05FFh EDCA Configuration 146*4882a593Smuzhiyun * 147*4882a593Smuzhiyun * ----------------------------------------------------- */ 148*4882a593Smuzhiyun #define REG_TXPAUSE_8812A 0x0522 149*4882a593Smuzhiyun #define REG_CTWND_8812 0x0572 150*4882a593Smuzhiyun #define REG_SECONDARY_CCA_CTRL_8812 0x0577 151*4882a593Smuzhiyun #define REG_SCH_TXCMD_8812A 0x05F8 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* ----------------------------------------------------- 154*4882a593Smuzhiyun * 155*4882a593Smuzhiyun * 0x0600h ~ 0x07FFh WMAC Configuration 156*4882a593Smuzhiyun * 157*4882a593Smuzhiyun * ----------------------------------------------------- */ 158*4882a593Smuzhiyun #define REG_MAC_CR_8812 0x0600 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define REG_MAC_TX_SM_STATE_8812 0x06B4 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* Power */ 163*4882a593Smuzhiyun #define REG_BFMER0_INFO_8812A 0x06E4 164*4882a593Smuzhiyun #define REG_BFMER1_INFO_8812A 0x06EC 165*4882a593Smuzhiyun #define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4 166*4882a593Smuzhiyun #define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8 167*4882a593Smuzhiyun #define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Hardware Port 2 */ 170*4882a593Smuzhiyun #define REG_BFMEE_SEL_8812A 0x0714 171*4882a593Smuzhiyun #define REG_SND_PTCL_CTRL_8812A 0x0718 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* ----------------------------------------------------- 175*4882a593Smuzhiyun * 176*4882a593Smuzhiyun * Redifine register definition for compatibility 177*4882a593Smuzhiyun * 178*4882a593Smuzhiyun * ----------------------------------------------------- */ 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* TODO: use these definition when using REG_xxx naming rule. 181*4882a593Smuzhiyun * NOTE: DO NOT Remove these definition. Use later. */ 182*4882a593Smuzhiyun #define ISR_8812 REG_HISR0_8812 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 185*4882a593Smuzhiyun * 8195 IMR/ISR bits (offset 0xB0, 8bits) 186*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 187*4882a593Smuzhiyun #define IMR_DISABLED_8812 0 188*4882a593Smuzhiyun /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 189*4882a593Smuzhiyun #define IMR_TIMER2_8812 BIT31 /* Timeout interrupt 2 */ 190*4882a593Smuzhiyun #define IMR_TIMER1_8812 BIT30 /* Timeout interrupt 1 */ 191*4882a593Smuzhiyun #define IMR_PSTIMEOUT_8812 BIT29 /* Power Save Time Out Interrupt */ 192*4882a593Smuzhiyun #define IMR_GTINT4_8812 BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 193*4882a593Smuzhiyun #define IMR_GTINT3_8812 BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 194*4882a593Smuzhiyun #define IMR_TXBCN0ERR_8812 BIT26 /* Transmit Beacon0 Error */ 195*4882a593Smuzhiyun #define IMR_TXBCN0OK_8812 BIT25 /* Transmit Beacon0 OK */ 196*4882a593Smuzhiyun #define IMR_TSF_BIT32_TOGGLE_8812 BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 197*4882a593Smuzhiyun #define IMR_BCNDMAINT0_8812 BIT20 /* Beacon DMA Interrupt 0 */ 198*4882a593Smuzhiyun #define IMR_BCNDERR0_8812 BIT16 /* Beacon Queue DMA OK0 */ 199*4882a593Smuzhiyun #define IMR_HSISR_IND_ON_INT_8812 BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 200*4882a593Smuzhiyun #define IMR_BCNDMAINT_E_8812 BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 201*4882a593Smuzhiyun #define IMR_ATIMEND_8812 BIT12 /* CTWidnow End or ATIM Window End */ 202*4882a593Smuzhiyun #define IMR_C2HCMD_8812 BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 203*4882a593Smuzhiyun #define IMR_CPWM2_8812 BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 204*4882a593Smuzhiyun #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 205*4882a593Smuzhiyun #define IMR_HIGHDOK_8812 BIT7 /* High Queue DMA OK */ 206*4882a593Smuzhiyun #define IMR_MGNTDOK_8812 BIT6 /* Management Queue DMA OK */ 207*4882a593Smuzhiyun #define IMR_BKDOK_8812 BIT5 /* AC_BK DMA OK */ 208*4882a593Smuzhiyun #define IMR_BEDOK_8812 BIT4 /* AC_BE DMA OK */ 209*4882a593Smuzhiyun #define IMR_VIDOK_8812 BIT3 /* AC_VI DMA OK */ 210*4882a593Smuzhiyun #define IMR_VODOK_8812 BIT2 /* AC_VO DMA OK */ 211*4882a593Smuzhiyun #define IMR_RDU_8812 BIT1 /* Rx Descriptor Unavailable */ 212*4882a593Smuzhiyun #define IMR_ROK_8812 BIT0 /* Receive DMA OK */ 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 215*4882a593Smuzhiyun #define IMR_BCNDMAINT7_8812 BIT27 /* Beacon DMA Interrupt 7 */ 216*4882a593Smuzhiyun #define IMR_BCNDMAINT6_8812 BIT26 /* Beacon DMA Interrupt 6 */ 217*4882a593Smuzhiyun #define IMR_BCNDMAINT5_8812 BIT25 /* Beacon DMA Interrupt 5 */ 218*4882a593Smuzhiyun #define IMR_BCNDMAINT4_8812 BIT24 /* Beacon DMA Interrupt 4 */ 219*4882a593Smuzhiyun #define IMR_BCNDMAINT3_8812 BIT23 /* Beacon DMA Interrupt 3 */ 220*4882a593Smuzhiyun #define IMR_BCNDMAINT2_8812 BIT22 /* Beacon DMA Interrupt 2 */ 221*4882a593Smuzhiyun #define IMR_BCNDMAINT1_8812 BIT21 /* Beacon DMA Interrupt 1 */ 222*4882a593Smuzhiyun #define IMR_BCNDOK7_8812 BIT20 /* Beacon Queue DMA OK Interrup 7 */ 223*4882a593Smuzhiyun #define IMR_BCNDOK6_8812 BIT19 /* Beacon Queue DMA OK Interrup 6 */ 224*4882a593Smuzhiyun #define IMR_BCNDOK5_8812 BIT18 /* Beacon Queue DMA OK Interrup 5 */ 225*4882a593Smuzhiyun #define IMR_BCNDOK4_8812 BIT17 /* Beacon Queue DMA OK Interrup 4 */ 226*4882a593Smuzhiyun #define IMR_BCNDOK3_8812 BIT16 /* Beacon Queue DMA OK Interrup 3 */ 227*4882a593Smuzhiyun #define IMR_BCNDOK2_8812 BIT15 /* Beacon Queue DMA OK Interrup 2 */ 228*4882a593Smuzhiyun #define IMR_BCNDOK1_8812 BIT14 /* Beacon Queue DMA OK Interrup 1 */ 229*4882a593Smuzhiyun #define IMR_ATIMEND_E_8812 BIT13 /* ATIM Window End Extension for Win7 */ 230*4882a593Smuzhiyun #define IMR_TXERR_8812 BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 231*4882a593Smuzhiyun #define IMR_RXERR_8812 BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 232*4882a593Smuzhiyun #define IMR_TXFOVW_8812 BIT9 /* Transmit FIFO Overflow */ 233*4882a593Smuzhiyun #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */ 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 237*4882a593Smuzhiyun /* #define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */ 238*4882a593Smuzhiyun #define IMR_TX_MASK (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812) 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812) 243*4882a593Smuzhiyun #endif 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* **************************************************************************** 247*4882a593Smuzhiyun * Regsiter Bit and Content definition 248*4882a593Smuzhiyun * **************************************************************************** */ 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun /* 2 ACMHWCTRL 0x05C0 */ 251*4882a593Smuzhiyun #define AcmHw_HwEn_8812 BIT(0) 252*4882a593Smuzhiyun #define AcmHw_VoqEn_8812 BIT(1) 253*4882a593Smuzhiyun #define AcmHw_ViqEn_8812 BIT(2) 254*4882a593Smuzhiyun #define AcmHw_BeqEn_8812 BIT(3) 255*4882a593Smuzhiyun #define AcmHw_VoqStatus_8812 BIT(5) 256*4882a593Smuzhiyun #define AcmHw_ViqStatus_8812 BIT(6) 257*4882a593Smuzhiyun #define AcmHw_BeqStatus_8812 BIT(7) 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #endif /* __RTL8812A_SPEC_H__ */ 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #ifdef CONFIG_RTL8821A 262*4882a593Smuzhiyun #include "rtl8821a_spec.h" 263*4882a593Smuzhiyun #endif /* CONFIG_RTL8821A */ 264