1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8812A_SPEC_H__ 16 #define __RTL8812A_SPEC_H__ 17 18 #include <drv_conf.h> 19 20 21 /* ************************************************************ 22 * 8812 Regsiter offset definition 23 * ************************************************************ */ 24 25 /* ************************************************************ 26 * 27 * ************************************************************ */ 28 29 /* ----------------------------------------------------- 30 * 31 * 0x0000h ~ 0x00FFh System Configuration 32 * 33 * ----------------------------------------------------- */ 34 #define REG_SYS_CLKR_8812A 0x0008 35 #define REG_AFE_PLL_CTRL_8812A 0x0028 36 #define REG_HSIMR_8812 0x0058 37 #define REG_HSISR_8812 0x005c 38 #define REG_GPIO_EXT_CTRL 0x0060 39 #define REG_GPIO_STATUS_8812 0x006C 40 #define REG_SDIO_CTRL_8812 0x0070 41 #define REG_OPT_CTRL_8812 0x0074 42 #define REG_RF_B_CTRL_8812 0x0076 43 #define REG_FW_DRV_MSG_8812 0x0088 44 #define REG_HMEBOX_E2_E3_8812 0x008C 45 #define REG_HIMR0_8812 0x00B0 46 #define REG_HISR0_8812 0x00B4 47 #define REG_HIMR1_8812 0x00B8 48 #define REG_HISR1_8812 0x00BC 49 #define REG_EFUSE_BURN_GNT_8812 0x00CF 50 #define REG_SYS_CFG1_8812 0x00FC 51 52 /* ----------------------------------------------------- 53 * 54 * 0x0100h ~ 0x01FFh MACTOP General Configuration 55 * 56 * ----------------------------------------------------- */ 57 #define REG_CR_8812A 0x100 58 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) 59 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) 60 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) 61 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 62 63 #define REG_RSVD3_8812 0x0168 64 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 65 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 66 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 67 68 #define REG_HMEBOX_EXT0_8812 0x01F0 69 #define REG_HMEBOX_EXT1_8812 0x01F4 70 #define REG_HMEBOX_EXT2_8812 0x01F8 71 #define REG_HMEBOX_EXT3_8812 0x01FC 72 73 /* ----------------------------------------------------- 74 * 75 * 0x0200h ~ 0x027Fh TXDMA Configuration 76 * 77 * ----------------------------------------------------- */ 78 #define REG_DWBCN0_CTRL_8812 REG_TDECTRL 79 #define REG_DWBCN1_CTRL_8812 0x0228 80 81 /* ----------------------------------------------------- 82 * 83 * 0x0280h ~ 0x02FFh RXDMA Configuration 84 * 85 * ----------------------------------------------------- */ 86 #define REG_TDECTRL_8812A 0x0208 87 #define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/ 88 #define REG_RXDMA_PRO_8812 0x0290 89 #define REG_EARLY_MODE_CONTROL_8812 0x02BC 90 #define REG_RSVD5_8812 0x02F0 91 #define REG_RSVD6_8812 0x02F4 92 #define REG_RSVD7_8812 0x02F8 93 #define REG_RSVD8_8812 0x02FC 94 95 96 /* ----------------------------------------------------- 97 * 98 * 0x0300h ~ 0x03FFh PCIe 99 * 100 * ----------------------------------------------------- */ 101 #define REG_PCIE_CTRL_REG_8812A 0x0300 102 #define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */ 103 #define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */ 104 #define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ 105 #define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ 106 #define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */ 107 #define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */ 108 #define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ 109 #define REG_PCIE_HRPWM_8812A 0x0361 /* PCIe RPWM */ 110 #define REG_PCIE_HCPWM_8812A 0x0363 /* PCIe CPWM */ 111 112 #define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */ 113 114 /* ----------------------------------------------------- 115 * 116 * 0x0400h ~ 0x047Fh Protocol Configuration 117 * 118 * ----------------------------------------------------- */ 119 #define REG_TXPKT_EMPTY_8812A 0x041A 120 #define REG_FWHW_TXQ_CTRL_8812A 0x0420 121 #define REG_TXBF_CTRL_8812A 0x042C 122 #define REG_ARFR0_8812 0x0444 123 #define REG_ARFR1_8812 0x044C 124 #define REG_CCK_CHECK_8812 0x0454 125 #define REG_AMPDU_MAX_TIME_8812 0x0456 126 #define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457 127 128 #define REG_AMPDU_MAX_LENGTH_8812 0x0458 129 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D 130 #define REG_NDPA_OPT_CTRL_8812A 0x045F 131 #define REG_DATA_SC_8812 0x0483 132 #ifdef CONFIG_WOWLAN 133 #define REG_TXPKTBUF_IV_LOW 0x0484 134 #define REG_TXPKTBUF_IV_HIGH 0x0488 135 #endif 136 #define REG_ARFR2_8812 0x048C 137 #define REG_ARFR3_8812 0x0494 138 #define REG_TXRPT_START_OFFSET 0x04AC 139 #define REG_AMPDU_BURST_MODE_8812 0x04BC 140 #define REG_HT_SINGLE_AMPDU_8812 0x04C7 141 #define REG_MACID_PKT_DROP0_8812 0x04D0 142 143 /* ----------------------------------------------------- 144 * 145 * 0x0500h ~ 0x05FFh EDCA Configuration 146 * 147 * ----------------------------------------------------- */ 148 #define REG_TXPAUSE_8812A 0x0522 149 #define REG_CTWND_8812 0x0572 150 #define REG_SECONDARY_CCA_CTRL_8812 0x0577 151 #define REG_SCH_TXCMD_8812A 0x05F8 152 153 /* ----------------------------------------------------- 154 * 155 * 0x0600h ~ 0x07FFh WMAC Configuration 156 * 157 * ----------------------------------------------------- */ 158 #define REG_MAC_CR_8812 0x0600 159 160 #define REG_MAC_TX_SM_STATE_8812 0x06B4 161 162 /* Power */ 163 #define REG_BFMER0_INFO_8812A 0x06E4 164 #define REG_BFMER1_INFO_8812A 0x06EC 165 #define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4 166 #define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8 167 #define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC 168 169 /* Hardware Port 2 */ 170 #define REG_BFMEE_SEL_8812A 0x0714 171 #define REG_SND_PTCL_CTRL_8812A 0x0718 172 173 174 /* ----------------------------------------------------- 175 * 176 * Redifine register definition for compatibility 177 * 178 * ----------------------------------------------------- */ 179 180 /* TODO: use these definition when using REG_xxx naming rule. 181 * NOTE: DO NOT Remove these definition. Use later. */ 182 #define ISR_8812 REG_HISR0_8812 183 184 /* ---------------------------------------------------------------------------- 185 * 8195 IMR/ISR bits (offset 0xB0, 8bits) 186 * ---------------------------------------------------------------------------- */ 187 #define IMR_DISABLED_8812 0 188 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 189 #define IMR_TIMER2_8812 BIT31 /* Timeout interrupt 2 */ 190 #define IMR_TIMER1_8812 BIT30 /* Timeout interrupt 1 */ 191 #define IMR_PSTIMEOUT_8812 BIT29 /* Power Save Time Out Interrupt */ 192 #define IMR_GTINT4_8812 BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 193 #define IMR_GTINT3_8812 BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 194 #define IMR_TXBCN0ERR_8812 BIT26 /* Transmit Beacon0 Error */ 195 #define IMR_TXBCN0OK_8812 BIT25 /* Transmit Beacon0 OK */ 196 #define IMR_TSF_BIT32_TOGGLE_8812 BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 197 #define IMR_BCNDMAINT0_8812 BIT20 /* Beacon DMA Interrupt 0 */ 198 #define IMR_BCNDERR0_8812 BIT16 /* Beacon Queue DMA OK0 */ 199 #define IMR_HSISR_IND_ON_INT_8812 BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 200 #define IMR_BCNDMAINT_E_8812 BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 201 #define IMR_ATIMEND_8812 BIT12 /* CTWidnow End or ATIM Window End */ 202 #define IMR_C2HCMD_8812 BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 203 #define IMR_CPWM2_8812 BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 204 #define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 205 #define IMR_HIGHDOK_8812 BIT7 /* High Queue DMA OK */ 206 #define IMR_MGNTDOK_8812 BIT6 /* Management Queue DMA OK */ 207 #define IMR_BKDOK_8812 BIT5 /* AC_BK DMA OK */ 208 #define IMR_BEDOK_8812 BIT4 /* AC_BE DMA OK */ 209 #define IMR_VIDOK_8812 BIT3 /* AC_VI DMA OK */ 210 #define IMR_VODOK_8812 BIT2 /* AC_VO DMA OK */ 211 #define IMR_RDU_8812 BIT1 /* Rx Descriptor Unavailable */ 212 #define IMR_ROK_8812 BIT0 /* Receive DMA OK */ 213 214 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 215 #define IMR_BCNDMAINT7_8812 BIT27 /* Beacon DMA Interrupt 7 */ 216 #define IMR_BCNDMAINT6_8812 BIT26 /* Beacon DMA Interrupt 6 */ 217 #define IMR_BCNDMAINT5_8812 BIT25 /* Beacon DMA Interrupt 5 */ 218 #define IMR_BCNDMAINT4_8812 BIT24 /* Beacon DMA Interrupt 4 */ 219 #define IMR_BCNDMAINT3_8812 BIT23 /* Beacon DMA Interrupt 3 */ 220 #define IMR_BCNDMAINT2_8812 BIT22 /* Beacon DMA Interrupt 2 */ 221 #define IMR_BCNDMAINT1_8812 BIT21 /* Beacon DMA Interrupt 1 */ 222 #define IMR_BCNDOK7_8812 BIT20 /* Beacon Queue DMA OK Interrup 7 */ 223 #define IMR_BCNDOK6_8812 BIT19 /* Beacon Queue DMA OK Interrup 6 */ 224 #define IMR_BCNDOK5_8812 BIT18 /* Beacon Queue DMA OK Interrup 5 */ 225 #define IMR_BCNDOK4_8812 BIT17 /* Beacon Queue DMA OK Interrup 4 */ 226 #define IMR_BCNDOK3_8812 BIT16 /* Beacon Queue DMA OK Interrup 3 */ 227 #define IMR_BCNDOK2_8812 BIT15 /* Beacon Queue DMA OK Interrup 2 */ 228 #define IMR_BCNDOK1_8812 BIT14 /* Beacon Queue DMA OK Interrup 1 */ 229 #define IMR_ATIMEND_E_8812 BIT13 /* ATIM Window End Extension for Win7 */ 230 #define IMR_TXERR_8812 BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 231 #define IMR_RXERR_8812 BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 232 #define IMR_TXFOVW_8812 BIT9 /* Transmit FIFO Overflow */ 233 #define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */ 234 235 236 #ifdef CONFIG_PCI_HCI 237 /* #define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */ 238 #define IMR_TX_MASK (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812) 239 240 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812) 241 242 #define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812) 243 #endif 244 245 246 /* **************************************************************************** 247 * Regsiter Bit and Content definition 248 * **************************************************************************** */ 249 250 /* 2 ACMHWCTRL 0x05C0 */ 251 #define AcmHw_HwEn_8812 BIT(0) 252 #define AcmHw_VoqEn_8812 BIT(1) 253 #define AcmHw_ViqEn_8812 BIT(2) 254 #define AcmHw_BeqEn_8812 BIT(3) 255 #define AcmHw_VoqStatus_8812 BIT(5) 256 #define AcmHw_ViqStatus_8812 BIT(6) 257 #define AcmHw_BeqStatus_8812 BIT(7) 258 259 #endif /* __RTL8812A_SPEC_H__ */ 260 261 #ifdef CONFIG_RTL8821A 262 #include "rtl8821a_spec.h" 263 #endif /* CONFIG_RTL8821A */ 264