Searched hist:f2d6b4ee5740245a92fd511180f7eebc6736a80b (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | neoverse_n1.h | f2d6b4ee5740245a92fd511180f7eebc6736a80b Fri Jan 24 11:54:44 UTC 2020 Manish Pandey <manish.pandey2@arm.com> Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | neoverse_n1.S | f2d6b4ee5740245a92fd511180f7eebc6736a80b Fri Jan 24 11:54:44 UTC 2020 Manish Pandey <manish.pandey2@arm.com> Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | f2d6b4ee5740245a92fd511180f7eebc6736a80b Fri Jan 24 11:54:44 UTC 2020 Manish Pandey <manish.pandey2@arm.com> Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | f2d6b4ee5740245a92fd511180f7eebc6736a80b Fri Jan 24 11:54:44 UTC 2020 Manish Pandey <manish.pandey2@arm.com> Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
|