Searched hist:e26c59d2c968eb0122bf1c333d5ceba534d5fe45 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a78.h | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 Tue Oct 06 22:55:25 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a78.S | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 Tue Oct 06 22:55:25 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 Tue Oct 06 22:55:25 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 Tue Oct 06 22:55:25 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
|