Searched hist:dcbfbcb5de2c0110cf397dae62a4f6cf7ad2a6a2 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a76.h | dcbfbcb5de2c0110cf397dae62a4f6cf7ad2a6a2 Tue Jun 02 20:02:28 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a76.S | dcbfbcb5de2c0110cf397dae62a4f6cf7ad2a6a2 Tue Jun 02 20:02:28 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
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| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | dcbfbcb5de2c0110cf397dae62a4f6cf7ad2a6a2 Tue Jun 02 20:02:28 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | dcbfbcb5de2c0110cf397dae62a4f6cf7ad2a6a2 Tue Jun 02 20:02:28 UTC 2020 johpow01 <john.powell@arm.com> Workaround for Cortex A76 erratum 1800710
Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
|