Searched hist:d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/services/std_svc/errata_abi/ |
| H A D | errata_abi_main.c | d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 Tue Oct 17 12:55:55 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a710.S | d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 Tue Oct 17 12:55:55 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 Tue Oct 17 12:55:55 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 Tue Oct 17 12:55:55 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|