Searched hist:af5ae9a73f67dc8c9ed493846d031b052b0f22a0 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a720_ae.h | af5ae9a73f67dc8c9ed493846d031b052b0f22a0 Tue Jan 21 23:23:26 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a720_ae.S | af5ae9a73f67dc8c9ed493846d031b052b0f22a0 Tue Jan 21 23:23:26 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | errata_common.c | af5ae9a73f67dc8c9ed493846d031b052b0f22a0 Tue Jan 21 23:23:26 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| H A D | cpu-ops.mk | af5ae9a73f67dc8c9ed493846d031b052b0f22a0 Tue Jan 21 23:23:26 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 845213ed0ddb08be79f621990db1314f4988d2e5 Wed Feb 19 15:37:35 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): fix a typo in errata doc
Commit@af5ae9a73f67dc8c9ed493846d031b052b0f22a0
Adding a Cortex-A720-AE erratum 3699562 has a typo in CPU name
for the errata, it is for Cortex-A720-AE but had incorrectly
mentioned as Cortex-A715_AE.
Change-Id: I2332a3fcaf56a7aaab5a04e3d40428cc746d2d46
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
af5ae9a73f67dc8c9ed493846d031b052b0f22a0 Tue Jan 21 23:23:26 UTC 2025 Govindraj Raja <govindraj.raja@arm.com> fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|