18118078bSAhmed Azeem/* 2af5ae9a7SGovindraj Raja * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 38118078bSAhmed Azeem * 48118078bSAhmed Azeem * SPDX-License-Identifier: BSD-3-Clause 58118078bSAhmed Azeem */ 68118078bSAhmed Azeem 78118078bSAhmed Azeem#include <arch.h> 88118078bSAhmed Azeem#include <asm_macros.S> 98118078bSAhmed Azeem#include <common/bl_common.h> 108118078bSAhmed Azeem#include <cortex_a720_ae.h> 118118078bSAhmed Azeem#include <cpu_macros.S> 128118078bSAhmed Azeem#include <plat_macros.S> 138118078bSAhmed Azeem 148118078bSAhmed Azeem/* Hardware handled coherency */ 158118078bSAhmed Azeem#if HW_ASSISTED_COHERENCY == 0 168118078bSAhmed Azeem#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled" 178118078bSAhmed Azeem#endif 188118078bSAhmed Azeem 198118078bSAhmed Azeem/* 64-bit only core */ 208118078bSAhmed Azeem#if CTX_INCLUDE_AARCH32_REGS == 1 218118078bSAhmed Azeem#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 228118078bSAhmed Azeem#endif 238118078bSAhmed Azeem 2489dba82dSBoyan Karatotevcpu_reset_prologue cortex_a720_ae 2589dba82dSBoyan Karatotev 26af5ae9a7SGovindraj Raja.global check_erratum_cortex_a720_ae_3699562 27af5ae9a7SGovindraj Raja 2889dba82dSBoyan Karatotevadd_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562 29af5ae9a7SGovindraj Raja 30af5ae9a7SGovindraj Rajacheck_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0) 31af5ae9a7SGovindraj Raja 328118078bSAhmed Azeemcpu_reset_func_start cortex_a720_ae 338118078bSAhmed Azeem /* Disable speculative loads */ 348118078bSAhmed Azeem msr SSBS, xzr 35*2590e819SBoyan Karatotev enable_mpmm 368118078bSAhmed Azeemcpu_reset_func_end cortex_a720_ae 378118078bSAhmed Azeem 388118078bSAhmed Azeem /* ---------------------------------------------------- 398118078bSAhmed Azeem * HW will do the cache maintenance while powering down 408118078bSAhmed Azeem * ---------------------------------------------------- 418118078bSAhmed Azeem */ 428118078bSAhmed Azeemfunc cortex_a720_ae_core_pwr_dwn 438118078bSAhmed Azeem /* --------------------------------------------------- 448118078bSAhmed Azeem * Enable CPU power down bit in power control register 458118078bSAhmed Azeem * --------------------------------------------------- 468118078bSAhmed Azeem */ 478118078bSAhmed Azeem sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 488118078bSAhmed Azeem 498118078bSAhmed Azeem isb 508118078bSAhmed Azeem ret 518118078bSAhmed Azeemendfunc cortex_a720_ae_core_pwr_dwn 528118078bSAhmed Azeem 538118078bSAhmed Azeem /* --------------------------------------------- 548118078bSAhmed Azeem * This function provides Cortex-A720AE specific 558118078bSAhmed Azeem * register information for crash reporting. 568118078bSAhmed Azeem * It needs to return with x6 pointing to 578118078bSAhmed Azeem * a list of register names in ascii and 588118078bSAhmed Azeem * x8 - x15 having values of registers to be 598118078bSAhmed Azeem * reported. 608118078bSAhmed Azeem * --------------------------------------------- 618118078bSAhmed Azeem */ 628118078bSAhmed Azeem.section .rodata.cortex_a720_ae_regs, "aS" 638118078bSAhmed Azeemcortex_a720_ae_regs: /* The ascii list of register names to be reported */ 648118078bSAhmed Azeem .asciz "cpuectlr_el1", "" 658118078bSAhmed Azeem 668118078bSAhmed Azeemfunc cortex_a720_ae_cpu_reg_dump 678118078bSAhmed Azeem adr x6, cortex_a720_ae_regs 688118078bSAhmed Azeem mrs x8, CORTEX_A720_AE_CPUECTLR_EL1 698118078bSAhmed Azeem ret 708118078bSAhmed Azeemendfunc cortex_a720_ae_cpu_reg_dump 718118078bSAhmed Azeem 728118078bSAhmed Azeemdeclare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \ 738118078bSAhmed Azeem cortex_a720_ae_reset_func, \ 748118078bSAhmed Azeem cortex_a720_ae_core_pwr_dwn 75