Home
last modified time | relevance | path

Searched hist:aa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Dcortex_a77.haa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c Tue Jul 14 19:18:34 UTC 2020 laurenw-arm <lauren.wehrmeister@arm.com> Workaround for Cortex A77 erratum 1508412

Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dcortex_a77.Saa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c Tue Jul 14 19:18:34 UTC 2020 laurenw-arm <lauren.wehrmeister@arm.com> Workaround for Cortex A77 erratum 1508412

Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
/rk3399_ARM-atf/docs/design/
H A Dcpu-specific-build-macros.rstaa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c Tue Jul 14 19:18:34 UTC 2020 laurenw-arm <lauren.wehrmeister@arm.com> Workaround for Cortex A77 erratum 1508412

Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
/rk3399_ARM-atf/lib/cpus/
H A Dcpu-ops.mkaa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c Tue Jul 14 19:18:34 UTC 2020 laurenw-arm <lauren.wehrmeister@arm.com> Workaround for Cortex A77 erratum 1508412

Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b