1f363deb6SBalint Dobszay /* 2*4c700c15SGovindraj Raja * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3f363deb6SBalint Dobszay * 4f363deb6SBalint Dobszay * SPDX-License-Identifier: BSD-3-Clause 5f363deb6SBalint Dobszay */ 6f363deb6SBalint Dobszay 7f363deb6SBalint Dobszay #ifndef CORTEX_A77_H 8f363deb6SBalint Dobszay #define CORTEX_A77_H 9f363deb6SBalint Dobszay 10f363deb6SBalint Dobszay #include <lib/utils_def.h> 11f363deb6SBalint Dobszay 12f363deb6SBalint Dobszay /* Cortex-A77 MIDR */ 13f363deb6SBalint Dobszay #define CORTEX_A77_MIDR U(0x410FD0D0) 14f363deb6SBalint Dobszay 151fe4a9d1SBipin Ravi /* Cortex-A77 loop count for CVE-2022-23960 mitigation */ 161fe4a9d1SBipin Ravi #define CORTEX_A77_BHB_LOOP_COUNT U(24) 171fe4a9d1SBipin Ravi 18f363deb6SBalint Dobszay /******************************************************************************* 19f363deb6SBalint Dobszay * CPU Extended Control register specific definitions. 20f363deb6SBalint Dobszay ******************************************************************************/ 21f363deb6SBalint Dobszay #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 2235c75377Sjohpow01 #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 2308e2fdbdSBoyan Karatotev #define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 24f363deb6SBalint Dobszay 25f363deb6SBalint Dobszay /******************************************************************************* 26f363deb6SBalint Dobszay * CPU Power Control register specific definitions. 27f363deb6SBalint Dobszay ******************************************************************************/ 28f363deb6SBalint Dobszay #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29f363deb6SBalint Dobszay #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) 30f363deb6SBalint Dobszay 313f0bec7cSjohpow01 /******************************************************************************* 323f0bec7cSjohpow01 * CPU Auxiliary Control register specific definitions. 333f0bec7cSjohpow01 ******************************************************************************/ 343f0bec7cSjohpow01 #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 353f0bec7cSjohpow01 #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 367bf1a7aaSBipin Ravi #define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) 373f0bec7cSjohpow01 38aa3efe3dSlaurenw-arm #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 39aa3efe3dSlaurenw-arm #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 40aa3efe3dSlaurenw-arm #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 41aa3efe3dSlaurenw-arm #define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 42aa3efe3dSlaurenw-arm #define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 43aa3efe3dSlaurenw-arm #define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 44aa3efe3dSlaurenw-arm 45f363deb6SBalint Dobszay #endif /* CORTEX_A77_H */ 46