Searched hist:"80942622 fe760c23f0a677eac48aff37e90f4251" (Results 1 – 7 of 7) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | neoverse_n1.h | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|
| H A D | cpu_macros.S | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|
| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | ea_delegate.S | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | neoverse_n1.S | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|
| H A D | cpu_helpers.S | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 80942622fe760c23f0a677eac48aff37e90f4251 Tue Aug 20 20:51:24 UTC 2019 laurenw-arm <lauren.wehrmeister@arm.com> Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.
The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
|