Searched hist:"73 e16df2e83b818e119b404283e6b2c49d3cafb3" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 73e16df2e83b818e119b404283e6b2c49d3cafb3 Wed Sep 20 06:37:50 UTC 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Change-Id: I47cc95d7e2cbf026bc34042cef4c2fe636bae674
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 615514c16dee4d43bd584ea326a5a56ebcb89c85)
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 73e16df2e83b818e119b404283e6b2c49d3cafb3 Wed Sep 20 06:37:50 UTC 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Change-Id: I47cc95d7e2cbf026bc34042cef4c2fe636bae674
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 615514c16dee4d43bd584ea326a5a56ebcb89c85)
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