Searched hist:"6 d716a4b4588d0f73662e3b2527b92a12a877bc5" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/kernel/ |
| H A D | semihosting_rv.S | 6d716a4b4588d0f73662e3b2527b92a12a877bc5 Wed Feb 21 06:28:08 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Add semihosting.S for semihosting instructions
RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://github.com/riscv-non-isa/riscv-semihosting
Add semihosting.S into RISC-V kernel folder to implement the trap
instruction sequence.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| H A D | sub.mk | 6d716a4b4588d0f73662e3b2527b92a12a877bc5 Wed Feb 21 06:28:08 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Add semihosting.S for semihosting instructions
RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://github.com/riscv-non-isa/riscv-semihosting
Add semihosting.S into RISC-V kernel folder to implement the trap
instruction sequence.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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