Searched hist:"5993 af454fca84d1401d12eabc3c714b6b5dd953" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/ |
| H A D | cm3_system_reset.c | 5993af454fca84d1401d12eabc3c714b6b5dd953 Thu Apr 11 09:11:47 UTC 2024 Marek Behún <marek.behun@nic.cz> fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor
Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via the Cortex-M3 secure
coprocessor.
Recall that Turris MOX has a HW bug wherein a SoC reset initiated by
writing the magic value to the North Bridge Warm Reset register may
randomly freeze the board.
Back in 2021 we introduced the CM3_SYSTEM_RESET build option for the
Armada 3700 platform, which, when enabled, adds code to the PSCI reset
handler so that the SoC reset is done by requesting the firmware in the
Cortex-M3 secure coprocessor to do it, instead of writing the Warm Reset
register.
The secure coprocessor firmware tried various things to put the board
into a state where the SoC reset circuit would work correctly. This
managed to fix the issue for some boards, but not for all of them.
Another considered method to overcome this issue was to reset all the
SoC peripheral controllers one by one by writing to specific registers,
instead of triggering the SoC reset circuit via the Warm Reset register.
This method was not used because until now, there was one peripheral
that I could not find a way how to reset properly: the Generic Interrupt
Controller (GIC).
After 3 years I have finally found a way how to reset the GIC, and it
needs to be done by the main processor, before the secure coprocessor
resets the main processor.
Change-Id: Icc23251ef97738b6b48af514d5118440ec21cdd7
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
| H A D | plat_pm.c | 5993af454fca84d1401d12eabc3c714b6b5dd953 Thu Apr 11 09:11:47 UTC 2024 Marek Behún <marek.behun@nic.cz> fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor
Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via the Cortex-M3 secure
coprocessor.
Recall that Turris MOX has a HW bug wherein a SoC reset initiated by
writing the magic value to the North Bridge Warm Reset register may
randomly freeze the board.
Back in 2021 we introduced the CM3_SYSTEM_RESET build option for the
Armada 3700 platform, which, when enabled, adds code to the PSCI reset
handler so that the SoC reset is done by requesting the firmware in the
Cortex-M3 secure coprocessor to do it, instead of writing the Warm Reset
register.
The secure coprocessor firmware tried various things to put the board
into a state where the SoC reset circuit would work correctly. This
managed to fix the issue for some boards, but not for all of them.
Another considered method to overcome this issue was to reset all the
SoC peripheral controllers one by one by writing to specific registers,
instead of triggering the SoC reset circuit via the Warm Reset register.
This method was not used because until now, there was one peripheral
that I could not find a way how to reset properly: the Generic Interrupt
Controller (GIC).
After 3 years I have finally found a way how to reset the GIC, and it
needs to be done by the main processor, before the secure coprocessor
resets the main processor.
Change-Id: Icc23251ef97738b6b48af514d5118440ec21cdd7
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/include/ |
| H A D | a3700_pm.h | 5993af454fca84d1401d12eabc3c714b6b5dd953 Thu Apr 11 09:11:47 UTC 2024 Marek Behún <marek.behun@nic.cz> fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor
Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via the Cortex-M3 secure
coprocessor.
Recall that Turris MOX has a HW bug wherein a SoC reset initiated by
writing the magic value to the North Bridge Warm Reset register may
randomly freeze the board.
Back in 2021 we introduced the CM3_SYSTEM_RESET build option for the
Armada 3700 platform, which, when enabled, adds code to the PSCI reset
handler so that the SoC reset is done by requesting the firmware in the
Cortex-M3 secure coprocessor to do it, instead of writing the Warm Reset
register.
The secure coprocessor firmware tried various things to put the board
into a state where the SoC reset circuit would work correctly. This
managed to fix the issue for some boards, but not for all of them.
Another considered method to overcome this issue was to reset all the
SoC peripheral controllers one by one by writing to specific registers,
instead of triggering the SoC reset circuit via the Warm Reset register.
This method was not used because until now, there was one peripheral
that I could not find a way how to reset properly: the Generic Interrupt
Controller (GIC).
After 3 years I have finally found a way how to reset the GIC, and it
needs to be done by the main processor, before the secure coprocessor
resets the main processor.
Change-Id: Icc23251ef97738b6b48af514d5118440ec21cdd7
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|