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| H A D | neoverse_n2.S | 54b86d47eb05f09330df57519b7d04b9968890e5 Sun Dec 10 14:15:44 UTC 2023 Thomas Abraham <thomas.abraham@arm.com> fix(cpus): fix incorrect AMU trap settings for N2 CPU
The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
access of AMU registers from EL0/EL1 and EL2 respectively are
incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in
both the CPTR_EL2 and CPTR_EL3 registers.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8
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