Searched hist:"4 b412b507a1648e00fb68b06b8cbe88ac9239317" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| H A D | nvg.c | 4b412b507a1648e00fb68b06b8cbe88ac9239317 Sat Nov 04 23:36:23 UTC 2017 Vignesh Radhakrishnan <vigneshr@nvidia.com> Tegra194: mce: fix cg_cstate encoding format
This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info
- cg_cstate values can range from 0 to 7, with 7 representing cg7
- Thus, cg_cstate is to be encoded using 3 bits (val: 0-7)
- Fix this, as per ISS and ensure bits 8, 9, 10 are used
Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/include/ |
| H A D | mce_private.h | 4b412b507a1648e00fb68b06b8cbe88ac9239317 Sat Nov 04 23:36:23 UTC 2017 Vignesh Radhakrishnan <vigneshr@nvidia.com> Tegra194: mce: fix cg_cstate encoding format
This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info
- cg_cstate values can range from 0 to 7, with 7 representing cg7
- Thus, cg_cstate is to be encoded using 3 bits (val: 0-7)
- Fix this, as per ISS and ensure bits 8, 9, 10 are used
Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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