Searched hist:"45 b52c202f7173d7610e2ca667907a6e646e90fa" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch32/ |
| H A D | cortex_a57.h | 45b52c202f7173d7610e2ca667907a6e646e90fa Wed Aug 02 15:35:04 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch32/ |
| H A D | cortex_a57.S | 45b52c202f7173d7610e2ca667907a6e646e90fa Wed Aug 02 15:35:04 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a57.h | 45b52c202f7173d7610e2ca667907a6e646e90fa Wed Aug 02 15:35:04 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a57.S | 45b52c202f7173d7610e2ca667907a6e646e90fa Wed Aug 02 15:35:04 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 45b52c202f7173d7610e2ca667907a6e646e90fa Wed Aug 02 15:35:04 UTC 2017 Eleanor Bonnici <Eleanor.bonnici@arm.com> Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|