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Searched hist:"3 a7297c29334259bb12be4bf596ea3468b4ab9a0" (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3588.h3a7297c29334259bb12be4bf596ea3468b4ab9a0 Thu Apr 21 08:56:20 UTC 2022 Kever Yang <kever.yang@rock-chips.com> clk: rk3588: Init the PPLL to 1.1G

The pcie2 combophy clk output will have better quality in this setting.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3588.c3a7297c29334259bb12be4bf596ea3468b4ab9a0 Thu Apr 21 08:56:20 UTC 2022 Kever Yang <kever.yang@rock-chips.com> clk: rk3588: Init the PPLL to 1.1G

The pcie2 combophy clk output will have better quality in this setting.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442