Searched hist:"015 e1cd5572dab8546ecf025ed4bcc0af4484f86" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a65.S | 015e1cd5572dab8546ecf025ed4bcc0af4484f86 Thu Oct 16 23:28:16 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1179935
Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR_EL1[49] to 1. The bit
prevents translation table walks from allocating lines into the
L1 cache. This has a negligible impact on performance when an
L2 cache is present.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: Ie59a4897f849269a590d8fa2d25cceab5f2cba3c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 015e1cd5572dab8546ecf025ed4bcc0af4484f86 Thu Oct 16 23:28:16 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1179935
Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR_EL1[49] to 1. The bit
prevents translation table walks from allocating lines into the
L1 cache. This has a negligible impact on performance when an
L2 cache is present.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: Ie59a4897f849269a590d8fa2d25cceab5f2cba3c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 015e1cd5572dab8546ecf025ed4bcc0af4484f86 Thu Oct 16 23:28:16 UTC 2025 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65 erratum 1179935
Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR_EL1[49] to 1. The bit
prevents translation table walks from allocating lines into the
L1 cache. This has a negligible impact on performance when an
L2 cache is present.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: Ie59a4897f849269a590d8fa2d25cceab5f2cba3c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|