Home
last modified time | relevance | path

Searched +full:versal +full:- +full:8 (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/
H A Dgpio-zynq.txt2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
12 - clocks : Clock specifier (see clock bindings for details)
13 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupts : Interrupt specifier (see interrupt bindings for
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
5 * (C) Copyright 2019 - 2020, Xilinx, Inc.
22 #include <linux/pci-ecam.h>
42 #define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8
102 * struct xilinx_cpm_pcie_port - PCIe port information
127 return readl_relaxed(port->reg_base + reg); in pcie_read()
133 writel_relaxed(val, port->reg_base + reg); in pcie_write()
147 dev_dbg(port->dev, "Requester ID %lu\n", in cpm_pcie_clear_err_interrupts()
161 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT); in xilinx_cpm_mask_leg_irq()
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/zynqmp/
H A Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
60 * struct zynqmp_clock - Clock
88 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
148 return -ENODEV; in zynqmp_is_valid_clock()
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
[all …]
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
[all …]
/OK3568_Linux_fs/buildroot/dl/uboot-tools/
HDu-boot-2021.07.tar.bz2 ... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
/OK3568_Linux_fs/recovery/
HDrootfs.cpio.gz ... then 81 /usr/share/command-not-found/command-not-found -- "$ ...