1*4882a593SmuzhiyunXilinx Zynq GPIO controller Device Tree Bindings 2*4882a593Smuzhiyun------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- #gpio-cells : Should be two 6*4882a593Smuzhiyun - First cell is the GPIO line number 7*4882a593Smuzhiyun - Second cell is used to specify optional 8*4882a593Smuzhiyun parameters (unused) 9*4882a593Smuzhiyun- compatible : Should be "xlnx,zynq-gpio-1.0" or 10*4882a593Smuzhiyun "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0 11*4882a593Smuzhiyun or "xlnx,pmc-gpio-1.0 12*4882a593Smuzhiyun- clocks : Clock specifier (see clock bindings for details) 13*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller. 14*4882a593Smuzhiyun- interrupts : Interrupt specifier (see interrupt bindings for 15*4882a593Smuzhiyun details) 16*4882a593Smuzhiyun- interrupt-controller : Marks the device node as an interrupt controller. 17*4882a593Smuzhiyun- #interrupt-cells : Should be 2. The first cell is the GPIO number. 18*4882a593Smuzhiyun The second cell bits[3:0] is used to specify trigger type and level flags: 19*4882a593Smuzhiyun 1 = low-to-high edge triggered. 20*4882a593Smuzhiyun 2 = high-to-low edge triggered. 21*4882a593Smuzhiyun 4 = active high level-sensitive. 22*4882a593Smuzhiyun 8 = active low level-sensitive. 23*4882a593Smuzhiyun- reg : Address and length of the register set for the device 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun gpio@e000a000 { 27*4882a593Smuzhiyun #gpio-cells = <2>; 28*4882a593Smuzhiyun compatible = "xlnx,zynq-gpio-1.0"; 29*4882a593Smuzhiyun clocks = <&clkc 42>; 30*4882a593Smuzhiyun gpio-controller; 31*4882a593Smuzhiyun interrupt-parent = <&intc>; 32*4882a593Smuzhiyun interrupts = <0 20 4>; 33*4882a593Smuzhiyun interrupt-controller; 34*4882a593Smuzhiyun #interrupt-cells = <2>; 35*4882a593Smuzhiyun reg = <0xe000a000 0x1000>; 36*4882a593Smuzhiyun }; 37