Searched +full:per +full:- +full:hart (Results 1 – 12 of 12) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause4 ---5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: SiFive Platform-Level Interrupt Controller (PLIC)11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller12 (PLIC) high-level specification in the RISC-V Privileged Architecture14 hart contexts in the system, via the external interrupt source in each hart.16 A hart context is a privilege mode in a hardware execution thread. For example,17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two[all …]
1 # SPDX-License-Identifier: GPL-2.0-only216 bool "J-Core integrated AIC" if COMPILE_TEST220 Support for the J-Core integrated AIC.231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.274 tristate "TS-4800 IRQ controller"279 Support for the TS-4800 FPGA IRQ controller446 bool "C-SKY Multi Processor Interrupt Controller"449 Say yes here to enable C-SKY SMP interrupt controller driver used[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local19 The clock frequency of CLINT is specified via "timebase-frequency" DT[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Analog Devices LTC2983 Multi-sensor Temperature system10 - Nuno Sá <nuno.sa@analog.com>13 Analog Devices LTC2983 Multi-Sensor Digital Temperature Measurement System14 https://www.analog.com/media/en/technical-documentation/data-sheets/2983fc.pdf19 - adi,ltc298327 adi,mux-delay-config-us:29 The LTC2983 performs 2 or 3 internal conversion cycles per temperature[all …]
8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf23 - hrtimer base infrastructure24 - timeofday and clock source management25 - clock event management26 - high resolution timer functionality27 - dynamic ticks31 ---------------------------40 - time ordered enqueueing into a rb-tree41 - independent of ticks (the processing is based on nanoseconds)[all …]
1 # SPDX-License-Identifier: GPL-2.0-only167 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,190 32-bit free running decrementing counters.244 bool "Integrator-AP timer driver" if COMPILE_TEST247 Enables support for the Integrator-AP timer.280 available on many OMAP-like platforms.289 It has a 64-bit counter with update rate up to 1000MHz.290 This counter is accessed via couple of 32-bit memory-mapped registers.309 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST313 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores[all …]
4 This document describes RCU-related publications, and is followed by19 with short-lived threads, such as the K42 research operating system.20 However, Linux has long-lived tasks, so more is needed.23 serialization, which is an RCU-like mechanism that relies on the presence27 that these overheads were not so expensive in the mid-80s. Nonetheless,28 passive serialization appears to be the first deferred-destruction30 has lapsed, so this approach may be used in non-GPL software, if desired.34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].36 this paper helped inspire the update-side batching used in the later38 a description of Argus that noted that use of out-of-date values can[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * ACPI-WMI mapping driver5 * Copyright (C) 2007-2008 Carlos Corbacho <carlos@strangeworlds.co.uk>9 * Copyright (c) 2001-2007 Anton Altaparmakov12 * WMI bus infrastructure by Andrew Lutomirski and Darren Hart:37 MODULE_DESCRIPTION("ACPI-WMI Mapping Driver");101 .name = "acpi-wmi",122 block = &wblock->gblock; in find_guid()124 if (memcmp(block->guid, &guid_input, 16) == 0) { in find_guid()141 if (wdriver->id_table == NULL) in find_guid_context()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later16 * PI-futex support started by Ingo Molnar and Thomas Gleixner23 * Requeue-PI support by Darren Hart <dvhltc@us.ibm.com>29 * Kirkwood for proof-of-concept implementation.40 #include <linux/fault-inject.h>102 * smp_mb(); (A) <-- paired with -.111 * `--------> smp_mb(); (B)118 * waiters--; (b) unlock(hash_bucket(futex));142 * acquiring the lock. It then decrements them again after releasing it -162 * NOMMU does not have per process address space. Let the compiler optimize[all …]
2 lrz - receive files with x/y/zmodem19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA20 02111-1307, USA.40 //#include "long-options.h"115 int tcp_socket=-1;176 if (!zi->fname) \179 shortname=strrchr(zi->fname,'/'); \181 shortname=zi->fname; \232 wait_msec -= xyzModem_CHAR_TIMEOUT; in read_data()486 {"allow-commands", no_argument, NULL, 'C'},[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
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