1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: SiFive Core Local Interruptor 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Palmer Dabbelt <palmer@dabbelt.com> 11*4882a593Smuzhiyun - Anup Patel <anup.patel@wdc.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: 14*4882a593Smuzhiyun SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15*4882a593Smuzhiyun Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16*4882a593Smuzhiyun interrupts. It directly connects to the timer and inter-processor interrupt 17*4882a593Smuzhiyun lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local 18*4882a593Smuzhiyun interrupt controller is the parent interrupt controller for CLINT device. 19*4882a593Smuzhiyun The clock frequency of CLINT is specified via "timebase-frequency" DT 20*4882a593Smuzhiyun property of "/cpus" DT node. The "timebase-frequency" DT property is 21*4882a593Smuzhiyun described in Documentation/devicetree/bindings/riscv/cpus.yaml 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunproperties: 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - const: sifive,fu540-c000-clint 27*4882a593Smuzhiyun - const: sifive,clint0 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun description: 30*4882a593Smuzhiyun Should be "sifive,<chip>-clint" and "sifive,clint<version>". 31*4882a593Smuzhiyun Supported compatible strings are - 32*4882a593Smuzhiyun "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated 33*4882a593Smuzhiyun onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive 34*4882a593Smuzhiyun CLINT v0 IP block with no chip integration tweaks. 35*4882a593Smuzhiyun Please refer to sifive-blocks-ip-versioning.txt for details 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun reg: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun interrupts-extended: 41*4882a593Smuzhiyun minItems: 1 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunadditionalProperties: false 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunrequired: 46*4882a593Smuzhiyun - compatible 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun - interrupts-extended 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunexamples: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun timer@2000000 { 53*4882a593Smuzhiyun compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 54*4882a593Smuzhiyun interrupts-extended = <&cpu1intc 3 &cpu1intc 7 55*4882a593Smuzhiyun &cpu2intc 3 &cpu2intc 7 56*4882a593Smuzhiyun &cpu3intc 3 &cpu3intc 7 57*4882a593Smuzhiyun &cpu4intc 3 &cpu4intc 7>; 58*4882a593Smuzhiyun reg = <0x2000000 0x10000>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun... 61