Searched +full:mips +full:- +full:cpc (Results 1 – 25 of 34) sorted by relevance
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1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: MIPS Cluster Power Controller10 Defines a location of the MIPS Cluster Power Controller registers.13 - Paul Burton <paulburton@kernel.org>17 const: mti,mips-cpc22 used to map the MIPS CPC registers block.26 - compatible[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Author: Paul Burton <paul.burton@mips.com>8 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h17 /* The base address of the CPC registers */21 * mips_cpc_default_phys_base - retrieve the default physical base address of22 * the CPC26 * implemented per-platform.31 * mips_cpc_probe - probe for a Cluster Power Controller34 * a CPC is successfully detected, else -errno.41 return -ENODEV; in mips_cpc_probe()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Author: Paul Burton <paul.burton@mips.com>104 #include <asm/mips-cm.h>105 #include <asm/mips-cpc.h>106 #include <asm/mips-gic.h>109 * mips_cps_numclusters - return the number of clusters present in the system126 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster148 * GCR_CONFIG via the redirect region, since the CPC is always in mips_cps_cluster_config()160 * mips_cps_numcores - return the number of cores present in a cluster176 * mips_cps_numiocu - return the number of IOCUs present in a cluster[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Author: Paul Burton <paul.burton@mips.com>11 * The CM & CPC can only handle coherence & power control on a per-core basis,13 * enter or exit states requiring CM or CPC assistance in unison.25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */32 * cps_pm_support_state - determine whether the system supports a PM state40 * cps_pm_enter_state - enter a PM state43 * Enter the given PM state. If coupled_coherence is non-zero then it is45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Author: Paul Burton <paul.burton@mips.com>24 * mips_dsemul() - 'Emulate' an instruction from a branch delay slot30 * Emulate or execute an arbitrary MIPS instruction within the context of41 * do_dsemulret() - Return from a delay slot 'emulation' frame47 * passed as the cpc parameter to mips_dsemul().61 * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame78 * dsemul_thread_rollback() - Rollback from an 'emulation' frame99 * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state103 * for delay slot 'emulation' book-keeping is freed. This is to be called[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Author: Paul Burton <paul.burton@mips.com>8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h21 /* The base address of the CM L2-only sync region */25 * __mips_cm_phys_base - retrieve the physical base address of the CM37 * mips_cm_is64 - determine CM register width42 * or vice-versa. This variable indicates the width of the memory accesses46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.51 * mips_cm_error_report - Report CM cache errors60 * mips_cm_probe - probe for a Coherence Manager[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Author: Paul Burton <paul.burton@mips.com>13 #include <asm/mips-cps.h>27 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc"); in mips_cpc_default_phys_base()39 * mips_cpc_phys_base - retrieve the physical base address of the CPC55 /* If the CPC is already enabled, leave it so */ in mips_cpc_phys_base()65 /* Enable the CPC, mapped at the default address */ in mips_cpc_phys_base()80 return -ENODEV; in mips_cpc_probe()84 return -ENXIO; in mips_cpc_probe()94 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_lock_other()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Author: Paul Burton <paul.burton@mips.com>13 #include <asm/asm-offsets.h>17 #include <asm/mips-cps.h>20 #include <asm/pm-cps.h>21 #include <asm/smp-cps.h>25 * cps_nc_entry_fn - type of a generated non-coherent state entry function27 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count29 * The code entering & exiting non-coherent states is generated at runtime32 * core-specific code particularly for cache routines. If coupled_coherence[all …]
1 # SPDX-License-Identifier: GPL-2.03 # Makefile for the Linux/MIPS kernel.6 extra-y := head.o vmlinux.lds8 obj-y += branch.o cmpxchg.o elf.o entry.o genex.o idle.o irq.o \14 obj-y += cpu-r3k-probe.o16 obj-y += cpu-probe.o20 CFLAGS_REMOVE_ftrace.o = -pg21 CFLAGS_REMOVE_early_printk.o = -pg22 CFLAGS_REMOVE_perf_event.o = -pg23 CFLAGS_REMOVE_perf_event_mipsxx.o = -pg[all …]
10 * MIPS R2 user space instruction emulator for MIPS R628 #include <asm/mips-r2-to-r6-emul.h>65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()101 return -SIGFPE; in mipsr6_emul()106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Author: Paul Burton <paul.burton@mips.com>17 #include <asm/mips-cps.h>20 #include <asm/pm-cps.h>22 #include <asm/smp-cps.h>73 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()112 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()126 /* Detect whether the CCA is unsuited to multi-core SMP */ in cps_prepare_cpus()131 /* The CCA is coherent, multi-core is fine */ in cps_prepare_cpus()136 /* CCA is not coherent, multi-core is not usable */ in cps_prepare_cpus()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Author: Paul Burton <paul.burton@mips.com>11 #include <asm/mips-cps.h>20 "0x04", "cpc", "0x06", "0x07"193 return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); in __mips_cm_phys_base()204 * If the L2-only sync region is already enabled then leave it at it's in __mips_cm_l2sync_phys_base()223 /* L2-only sync was introduced with CM major revision 6 */ in mips_cm_probe_l2sync()257 return -ENODEV; in mips_cm_probe()261 return -ENXIO; in mips_cm_probe()269 return -ENODEV; in mips_cm_probe()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Author: Paul Burton <paul.burton@mips.com>9 #include <asm/asm-offsets.h>49 * Set dest to non-zero if the core supports the MT ASE, else zero. If64 * Set dest to non-zero if the core supports MIPSr6 multithreading94 .section .text.cps-vec162 /* Skip core-level init if we started up coherent */166 /* Perform any further required core-level initialisation */271 /* Set exclusive TC, non-active, master */277 /* Set TC non-active, non-allocatable */[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/clock/boston-clock.h>5 #include <dt-bindings/gpio/gpio.h>6 #include <dt-bindings/interrupt-controller/irq.h>7 #include <dt-bindings/interrupt-controller/mips-gic.h>10 #address-cells = <1>;11 #size-cells = <1>;15 stdout-path = "uart0:115200";23 #address-cells = <1>;[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */3 * Carsten Langgaard, carstenl@mips.com4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.6 * Defines of the Malta board specific address-MAP, registers, etc.13 #include <asm/mips-boards/msc01_pci.h>16 /* Mips interrupt controller found in SOCit variations */55 * CPC Specific definitions71 * Malta RTC-device indirect register access.
1 #include <dt-bindings/interrupt-controller/mips-gic.h>2 #include <dt-bindings/gpio/gpio.h>5 #address-cells = <1>;6 #size-cells = <1>;7 compatible = "mediatek,mt7621-soc";11 compatible = "mips,mips1004Kc";15 compatible = "mips,mips1004Kc";20 #address-cells = <0>;21 #interrupt-cells = <1>;22 interrupt-controller;[all …]
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.9 #define pr_fmt(fmt) "mips-gic-timer: " fmt22 #include <asm/mips-cps.h>59 int cpu = cpumask_first(evt->cpumask); in gic_next_event()71 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()80 cd->event_handler(cd); in gic_compare_interrupt()94 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()95 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()98 cd->rating = 350; in gic_clockevent_cpu_init()99 cd->irq = gic_timer_irq; in gic_clockevent_cpu_init()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only14 #include <asm/smp-ops.h>15 #include <asm/mips-cps.h>16 #include <asm/mach-ralink/ralink_regs.h>17 #include <asm/mach-ralink/mt7621.h>110 panic("Cannot detect cpc address"); in mips_cpc_default_phys_base()115 rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); in ralink_of_remap()116 rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); in ralink_of_remap()131 soc_dev_attr->soc_id = "mt7621"; in soc_dev_init()132 soc_dev_attr->family = "Ralink"; in soc_dev_init()[all …]
1 # SPDX-License-Identifier: GPL-2.02 config MIPS config125 bool "Generic board-agnostic MIPS kernel"212 Support for the Texas Instruments AR7 System-on-a-Chip283 Build a generic DT-based kernel image that boots on select284 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top376 This enables support for DEC's MIPS based workstations. For details377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the378 DECstation porting pages on <http://decstation.unix-ag.org/>.414 This a family of machines based on the MIPS R4030 chipset which was[all …]
5 Copyright (C) 1991-2021 Free Software Foundation, Inc.10 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover14 INFO-DIR-SECTION Software development15 START-INFO-DIR-ENTRY18 END-INFO-DIR-ENTRY27 the A-profile Architecture 10.3-2021.07 (arm-10.29)) version 2.36.1.36 * Invoking:: Command-Line Options56 Command-Line Options: Invoking.58 as [-a[cdghlns][=FILE]] [-alternate] [-D]59 [-compress-debug-sections] [-nocompress-debug-sections][all …]
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