1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Carsten Langgaard, carstenl@mips.com
4*4882a593Smuzhiyun * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Defines of the Malta board specific address-MAP, registers, etc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #ifndef __ASM_MIPS_BOARDS_MALTA_H
9*4882a593Smuzhiyun #define __ASM_MIPS_BOARDS_MALTA_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/addrspace.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/mips-boards/msc01_pci.h>
14*4882a593Smuzhiyun #include <asm/gt64120.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Mips interrupt controller found in SOCit variations */
17*4882a593Smuzhiyun #define MIPS_MSC01_IC_REG_BASE 0x1bc40000
18*4882a593Smuzhiyun #define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
22*4882a593Smuzhiyun * Bonito system controllers.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
25*4882a593Smuzhiyun #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
26*4882a593Smuzhiyun #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
27*4882a593Smuzhiyun
get_gt_port_base(unsigned long reg)28*4882a593Smuzhiyun static inline unsigned long get_gt_port_base(unsigned long reg)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun unsigned long addr;
31*4882a593Smuzhiyun addr = GT_READ(reg);
32*4882a593Smuzhiyun return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
get_msc_port_base(unsigned long reg)35*4882a593Smuzhiyun static inline unsigned long get_msc_port_base(unsigned long reg)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun unsigned long addr;
38*4882a593Smuzhiyun MSC_READ(reg, addr);
39*4882a593Smuzhiyun return (unsigned long) ioremap(addr, 0x10000);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * GCMP Specific definitions
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun #define GCMP_BASE_ADDR 0x1fbf8000
46*4882a593Smuzhiyun #define GCMP_ADDRSPACE_SZ (256 * 1024)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * GIC Specific definitions
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun #define GIC_BASE_ADDR 0x1bdc0000
52*4882a593Smuzhiyun #define GIC_ADDRSPACE_SZ (128 * 1024)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * CPC Specific definitions
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun #define CPC_BASE_ADDR 0x1bde0000
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * MSC01 BIU Specific definitions
61*4882a593Smuzhiyun * FIXME : These should be elsewhere ?
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun #define MSC01_BIU_REG_BASE 0x1bc80000
64*4882a593Smuzhiyun #define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
65*4882a593Smuzhiyun #define MSC01_SC_CFG_OFS 0x0110
66*4882a593Smuzhiyun #define MSC01_SC_CFG_GICPRES_MSK 0x00000004
67*4882a593Smuzhiyun #define MSC01_SC_CFG_GICPRES_SHF 2
68*4882a593Smuzhiyun #define MSC01_SC_CFG_GICENA_SHF 3
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Malta RTC-device indirect register access.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun #define MALTA_RTC_ADR_REG 0x70
74*4882a593Smuzhiyun #define MALTA_RTC_DAT_REG 0x71
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * Malta SMSC FDC37M817 Super I/O Controller register.
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun #define SMSC_CONFIG_REG 0x3f0
80*4882a593Smuzhiyun #define SMSC_DATA_REG 0x3f1
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define SMSC_CONFIG_DEVNUM 0x7
83*4882a593Smuzhiyun #define SMSC_CONFIG_ACTIVATE 0x30
84*4882a593Smuzhiyun #define SMSC_CONFIG_ENTER 0x55
85*4882a593Smuzhiyun #define SMSC_CONFIG_EXIT 0xaa
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define SMSC_CONFIG_DEVNUM_FLOPPY 0
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define SMSC_CONFIG_ACTIVATE_ENABLE 1
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define SMSC_WRITE(x, a) outb(x, a)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define MALTA_JMPRS_REG 0x1f000210
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun extern void __init *malta_dt_shim(void *fdt);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #endif /* __ASM_MIPS_BOARDS_MALTA_H */
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