Searched full:imx7ulp_clk_firc_bus_clk (Results 1 – 5 of 5) sorted by relevance
262 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;278 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,310 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
56 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
56 #define IMX7ULP_CLK_FIRC_BUS_CLK 42 macro
103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
126 …hws[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_hw_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8… in imx7ulp_clk_scg1_init()