1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017~2018 NXP 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_IMX7ULP_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* SCG1 */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IMX7ULP_CLK_DUMMY 0 14*4882a593Smuzhiyun #define IMX7ULP_CLK_ROSC 1 15*4882a593Smuzhiyun #define IMX7ULP_CLK_SOSC 2 16*4882a593Smuzhiyun #define IMX7ULP_CLK_FIRC 3 17*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PRE_SEL 4 18*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PRE_DIV 5 19*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL 6 20*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_POST_DIV1 7 21*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_POST_DIV2 8 22*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD0 9 23*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD1 10 24*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD2 11 25*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD3 12 26*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_PFD_SEL 13 27*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_SEL 14 28*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PRE_SEL 15 29*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PRE_DIV 16 30*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL 17 31*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_POST_DIV1 18 32*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_POST_DIV2 19 33*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD0 20 34*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD1 21 35*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD2 22 36*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD3 23 37*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_PFD_SEL 24 38*4882a593Smuzhiyun #define IMX7ULP_CLK_APLL_SEL 25 39*4882a593Smuzhiyun #define IMX7ULP_CLK_UPLL 26 40*4882a593Smuzhiyun #define IMX7ULP_CLK_SYS_SEL 27 41*4882a593Smuzhiyun #define IMX7ULP_CLK_CORE_DIV 28 42*4882a593Smuzhiyun #define IMX7ULP_CLK_BUS_DIV 29 43*4882a593Smuzhiyun #define IMX7ULP_CLK_PLAT_DIV 30 44*4882a593Smuzhiyun #define IMX7ULP_CLK_DDR_SEL 31 45*4882a593Smuzhiyun #define IMX7ULP_CLK_DDR_DIV 32 46*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC_SEL 33 47*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC0_DIV 34 48*4882a593Smuzhiyun #define IMX7ULP_CLK_GPU_DIV 35 49*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC1_DIV 36 50*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC1_BUS_DIV 37 51*4882a593Smuzhiyun #define IMX7ULP_CLK_NIC1_EXT_DIV 38 52*4882a593Smuzhiyun /* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ 53*4882a593Smuzhiyun #define IMX7ULP_CLK_MIPI_PLL 39 54*4882a593Smuzhiyun #define IMX7ULP_CLK_SIRC 40 55*4882a593Smuzhiyun #define IMX7ULP_CLK_SOSC_BUS_CLK 41 56*4882a593Smuzhiyun #define IMX7ULP_CLK_FIRC_BUS_CLK 42 57*4882a593Smuzhiyun #define IMX7ULP_CLK_SPLL_BUS_CLK 43 58*4882a593Smuzhiyun #define IMX7ULP_CLK_HSRUN_SYS_SEL 44 59*4882a593Smuzhiyun #define IMX7ULP_CLK_HSRUN_CORE_DIV 45 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define IMX7ULP_CLK_CORE 46 62*4882a593Smuzhiyun #define IMX7ULP_CLK_HSRUN_CORE 47 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define IMX7ULP_CLK_SCG1_END 48 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* PCC2 */ 67*4882a593Smuzhiyun #define IMX7ULP_CLK_DMA1 0 68*4882a593Smuzhiyun #define IMX7ULP_CLK_RGPIO2P1 1 69*4882a593Smuzhiyun #define IMX7ULP_CLK_FLEXBUS 2 70*4882a593Smuzhiyun #define IMX7ULP_CLK_SEMA42_1 3 71*4882a593Smuzhiyun #define IMX7ULP_CLK_DMA_MUX1 4 72*4882a593Smuzhiyun #define IMX7ULP_CLK_CAAM 6 73*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM4 7 74*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM5 8 75*4882a593Smuzhiyun #define IMX7ULP_CLK_LPIT1 9 76*4882a593Smuzhiyun #define IMX7ULP_CLK_LPSPI2 10 77*4882a593Smuzhiyun #define IMX7ULP_CLK_LPSPI3 11 78*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C4 12 79*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C5 13 80*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART4 14 81*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART5 15 82*4882a593Smuzhiyun #define IMX7ULP_CLK_FLEXIO1 16 83*4882a593Smuzhiyun #define IMX7ULP_CLK_USB0 17 84*4882a593Smuzhiyun #define IMX7ULP_CLK_USB1 18 85*4882a593Smuzhiyun #define IMX7ULP_CLK_USB_PHY 19 86*4882a593Smuzhiyun #define IMX7ULP_CLK_USB_PL301 20 87*4882a593Smuzhiyun #define IMX7ULP_CLK_USDHC0 21 88*4882a593Smuzhiyun #define IMX7ULP_CLK_USDHC1 22 89*4882a593Smuzhiyun #define IMX7ULP_CLK_WDG1 23 90*4882a593Smuzhiyun #define IMX7ULP_CLK_WDG2 24 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define IMX7ULP_CLK_PCC2_END 25 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* PCC3 */ 95*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM6 0 96*4882a593Smuzhiyun #define IMX7ULP_CLK_LPTPM7 1 97*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C6 2 98*4882a593Smuzhiyun #define IMX7ULP_CLK_LPI2C7 3 99*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART6 4 100*4882a593Smuzhiyun #define IMX7ULP_CLK_LPUART7 5 101*4882a593Smuzhiyun #define IMX7ULP_CLK_VIU 6 102*4882a593Smuzhiyun #define IMX7ULP_CLK_DSI 7 103*4882a593Smuzhiyun #define IMX7ULP_CLK_LCDIF 8 104*4882a593Smuzhiyun #define IMX7ULP_CLK_MMDC 9 105*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLC 10 106*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLD 11 107*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLE 12 108*4882a593Smuzhiyun #define IMX7ULP_CLK_PCTLF 13 109*4882a593Smuzhiyun #define IMX7ULP_CLK_GPU3D 14 110*4882a593Smuzhiyun #define IMX7ULP_CLK_GPU2D 15 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define IMX7ULP_CLK_PCC3_END 16 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* SMC1 */ 115*4882a593Smuzhiyun #define IMX7ULP_CLK_ARM 0 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define IMX7ULP_CLK_SMC1_END 1 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ 120