1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX7ULP Watchdog Timer (WDT) Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "watchdog.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun enum: 18*4882a593Smuzhiyun - fsl,imx7ulp-wdt 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupts: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun assigned-clocks: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun assigned-clocks-parents: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun timeout-sec: true 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunrequired: 38*4882a593Smuzhiyun - compatible 39*4882a593Smuzhiyun - interrupts 40*4882a593Smuzhiyun - reg 41*4882a593Smuzhiyun - clocks 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunadditionalProperties: false 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunexamples: 46*4882a593Smuzhiyun - | 47*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 48*4882a593Smuzhiyun #include <dt-bindings/clock/imx7ulp-clock.h> 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun watchdog@403d0000 { 51*4882a593Smuzhiyun compatible = "fsl,imx7ulp-wdt"; 52*4882a593Smuzhiyun reg = <0x403d0000 0x10000>; 53*4882a593Smuzhiyun interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 54*4882a593Smuzhiyun clocks = <&pcc2 IMX7ULP_CLK_WDG1>; 55*4882a593Smuzhiyun assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; 56*4882a593Smuzhiyun assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; 57*4882a593Smuzhiyun timeout-sec = <40>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun... 61