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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rza1-ports.yaml39 "^gpio-[0-9]*$":
121 $ref: "#/additionalProperties/anyOf/0"
129 reg = <0xfcfe3000 0x4230>;
132 * A GPIO controller node, controlling 16 pins indexed from 0.
134 * 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
140 gpio-ranges = <&pinctrl 0 48 16>;
146 * Pin #0 on port #3 is configured as alternate function #6.
150 pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
172 * Pin #0 on port #4 is configured as alternate function #2
176 pinmux = <RZA1_PINMUX(4, 0, 2)>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr3001 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr4201 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Drs6001 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dam43xx-clocks.dtsi12 #clock-cells = <0>;
16 reg = <0x0040>;
20 #clock-cells = <0>;
24 reg = <0x0040>;
28 #clock-cells = <0>;
32 reg = <0x0040>;
36 #clock-cells = <0>;
44 #clock-cells = <0>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr7s72100.dtsi32 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
55 #clock-cells = <0>;
58 clock-frequency = <0>;
62 #clock-cells = <0>;
70 #clock-cells = <0>;
79 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
83 #clock-cells = <0>;
[all …]
H A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x0040>;
17 #clock-cells = <0>;
21 reg = <0x0040>;
25 #clock-cells = <0>;
29 reg = <0x0040>;
33 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_hwimg_raw_data_8852b.h36 0x704, 0x601E0100,
37 0x4000, 0x00000000,
38 0x4004, 0xCA014000,
39 0x4008, 0xC751D4F0,
40 0x400C, 0x44511475,
41 0x4010, 0x00000000,
42 0x4014, 0x00000000,
43 0x4018, 0x4F4C084B,
44 0x401C, 0x084A4E52,
45 0x4020, 0x4D504E4B,
[all …]
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_hwimg_raw_data_8852b.h36 0x704, 0x601E0100,
37 0x4000, 0x00000000,
38 0x4004, 0xCA014000,
39 0x4008, 0xC751D4F0,
40 0x400C, 0x44511475,
41 0x4010, 0x00000000,
42 0x4014, 0x00000000,
43 0x4018, 0x4F4C084B,
44 0x401C, 0x084A4E52,
45 0x4020, 0x4D504E4B,
[all …]
H A Dhalbb_cr_info_8852b.h29 #define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
30 #define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
31 #define UPD_5MHZ_CNT_EN_C 0x0000
32 #define UPD_5MHZ_CNT_EN_C_M 0x2
33 #define CLK_640M_EN_C 0x0000
34 #define CLK_640M_EN_C_M 0x4
35 #define RFC_CK_PHASE_SEL_C 0x0000
36 #define RFC_CK_PHASE_SEL_C_M 0x8
37 #define RFC_CKEN_C 0x0000
38 #define RFC_CKEN_C_M 0x10
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
398 base = of_iomap(np, 0); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlegacy/
H A D4965-mac.c81 /* the rest are 0 by default */
93 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { in il4965_rx_queue_reset()
106 for (i = 0; i < RX_QUEUE_SIZE; i++) in il4965_rx_queue_reset()
111 rxq->read = rxq->write = 0; in il4965_rx_queue_reset()
112 rxq->write_actual = 0; in il4965_rx_queue_reset()
113 rxq->free_count = 0; in il4965_rx_queue_reset()
122 u32 rb_timeout = 0; in il4965_rx_init()
130 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); in il4965_rx_init()
133 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); in il4965_rx_init()
144 * RB timeout 0x10 in il4965_rx_init()
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/vendor/nunicode/src/libnu/gen/
H A D_ducet.c6 * Combined length : 0,
22 -19864, -19863, -19862, -19861, -19860, 0, -19859, -19858, -19857, -19856, -19855, -19854,
51 -19532, -19531, -19530, -19529, 0, -19528, 15, 17, 22, 16, 24, 50,
79 -19397, -19396, 0, 0, 0, -19395, 69, 71, 69, 76, 79, 90,
81 12, 9, 9, 16, 9, 16, -19389, -19388, 16, -19387, 0, 0,
89 -19318, -19317, -19316, -19315, -19314, -19313, -19312, -19311, -19310, 0, 0, 0,
90 0, -19309, 1, 1, -19308, 1, 2, 21, 5, 32, 20, 26,
91 32, 32, 32, 36, 32, -19307, 0, 0, 0, 0, -19306, -19305,
92 0, 0, -19304, -19303, -19302, -19301, -19300, -19299, -19298, -19297, -19296, -19295,
93 -19294, -19293, 0, 0, 0, -19292, 0, 0, 0, 0, 0, 0,
[all …]