Lines Matching +full:0 +full:x4230
81 /* the rest are 0 by default */
93 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { in il4965_rx_queue_reset()
106 for (i = 0; i < RX_QUEUE_SIZE; i++) in il4965_rx_queue_reset()
111 rxq->read = rxq->write = 0; in il4965_rx_queue_reset()
112 rxq->write_actual = 0; in il4965_rx_queue_reset()
113 rxq->free_count = 0; in il4965_rx_queue_reset()
122 u32 rb_timeout = 0; in il4965_rx_init()
130 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); in il4965_rx_init()
133 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); in il4965_rx_init()
144 * RB timeout 0x10 in il4965_rx_init()
158 return 0; in il4965_rx_init()
226 return 0; in il4965_hw_nic_init()
258 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) { in il4965_rx_queue_restock()
283 if (rxq->write_actual != (rxq->write & ~0x7)) { in il4965_rx_queue_restock()
321 if (il->hw_params.rx_page_order > 0) in il4965_rx_allocate()
346 pci_map_page(il->pci_dev, page, 0, in il4965_rx_allocate()
410 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { in il4965_rx_queue_free()
433 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); in il4965_rxq_stop()
438 if (ret < 0) in il4965_rxq_stop()
441 return 0; in il4965_rxq_stop()
447 int idx = 0; in il4965_hwrate_to_mac80211_idx()
448 int band_offset = 0; in il4965_hwrate_to_mac80211_idx()
452 idx = (rate_n_flags & 0xff); in il4965_hwrate_to_mac80211_idx()
459 if (il_rates[idx].plcp == (rate_n_flags & 0xFF)) in il4965_hwrate_to_mac80211_idx()
480 u8 max_rssi = 0; in il4965_calc_rssi()
488 for (i = 0; i < 3; i++) in il4965_calc_rssi()
493 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], in il4965_calc_rssi()
504 u32 decrypt_out = 0; in il4965_translate_rx_status()
556 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out); in il4965_translate_rx_status()
596 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), in il4965_pass_packet_to_mac80211()
658 D_DROP("dsp size out of range [0,20]: %d\n", in il4965_hdl_rx()
665 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status)); in il4965_hdl_rx()
683 rx_status.flag = 0; in il4965_hdl_rx()
762 u16 passive_dwell = 0; in il4965_get_channels_for_scan()
763 u16 active_dwell = 0; in il4965_get_channels_for_scan()
769 return 0; in il4965_get_channels_for_scan()
777 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) { in il4965_get_channels_for_scan()
817 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel, in il4965_get_channels_for_scan()
839 for (i = 0; i < RATE_ANT_NUM - 1; i++) { in il4965_toggle_tx_ant()
840 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; in il4965_toggle_tx_ant()
857 u32 rate_flags = 0; in il4965_request_scan()
859 u16 rx_chain = 0; in il4965_request_scan()
861 u8 n_probes = 0; in il4965_request_scan()
882 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE); in il4965_request_scan()
896 scan->suspend_time = 0; in il4965_request_scan()
905 D_SCAN("suspend_time 0x%X beacon interval %d\n", in il4965_request_scan()
910 int i, p = 0; in il4965_request_scan()
912 for (i = 0; i < il->scan_request->n_ssids; i++) { in il4965_request_scan()
1001 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; in il4965_request_scan()
1017 if (scan->channel_count == 0) { in il4965_request_scan()
1060 il->stations[sta_id].tid[tid].tfds_in_queue = 0; in il4965_free_tfds_in_queue()
1064 #define IL_TX_QUEUE_MSK 0xfffff
1123 res = (chain_bitmap & BIT(0)) >> 0; in il4965_count_chain_bitmap()
1180 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain, in il4965_set_rxon_chain()
1183 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || in il4965_set_rxon_chain()
1210 int pos = 0; in il4965_dump_fh()
1211 size_t bufsz = 0; in il4965_dump_fh()
1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { in il4965_dump_fh()
1235 " %34s: 0X%08x\n", in il4965_dump_fh()
1243 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { in il4965_dump_fh()
1244 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]), in il4965_dump_fh()
1247 return 0; in il4965_dump_fh()
1276 int num_active_rx = 0; in il4965_rx_calc_noise()
1277 int total_silence = 0; in il4965_rx_calc_noise()
1403 memset(&il->_4965.accum_stats, 0, in il4965_hdl_c_stats()
1405 memset(&il->_4965.delta_stats, 0, in il4965_hdl_c_stats()
1407 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats)); in il4965_hdl_c_stats()
1423 * VO 0
1497 !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) in il4965_tx_cmd_build_basic()
1513 tx_cmd->tid_tspec = qc[0] & 0xf; in il4965_tx_cmd_build_basic()
1528 tx_cmd->timeout.pm_frame_timeout = 0; in il4965_tx_cmd_build_basic()
1531 tx_cmd->driver_txop = 0; in il4965_tx_cmd_build_basic()
1533 tx_cmd->next_frame_len = 0; in il4965_tx_cmd_build_basic()
1561 tx_cmd->initial_rate_idx = 0; in il4965_tx_cmd_build_rate()
1572 rate_idx = info->control.rates[0].idx; in il4965_tx_cmd_build_rate()
1573 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0 in il4965_tx_cmd_build_rate()
1582 rate_flags = 0; in il4965_tx_cmd_build_rate()
1659 u16 seq_number = 0; in il4965_tx_skb()
1663 u8 wait_write_ptr = 0; in il4965_tx_skb()
1664 u8 tid = 0; in il4965_tx_skb()
1731 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; in il4965_tx_skb()
1741 seq_number += 0x10; in il4965_tx_skb()
1772 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); in il4965_tx_skb()
1773 memset(tx_cmd, 0, sizeof(struct il_tx_cmd)); in il4965_tx_skb()
1827 if (secondlen > 0) { in il4965_tx_skb()
1837 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0); in il4965_tx_skb()
1842 0, 0); in il4965_tx_skb()
1848 txq->need_update = 0; in il4965_tx_skb()
1863 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence)); in il4965_tx_skb()
1864 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); in il4965_tx_skb()
1908 return 0; in il4965_tx_skb()
1923 return 0; in il4965_alloc_dma_ptr()
1933 memset(ptr, 0, sizeof(*ptr)); in il4965_free_dma_ptr()
1948 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) in il4965_hw_txq_ctx_free()
1997 il4965_txq_set_sched(il, 0); in il4965_txq_ctx_alloc()
2005 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { in il4965_txq_ctx_alloc()
2033 il4965_txq_set_sched(il, 0); in il4965_txq_ctx_reset()
2040 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) in il4965_txq_ctx_reset()
2053 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) in il4965_txq_ctx_unmap()
2068 _il_wr_prph(il, IL49_SCD_TXFACT, 0); in il4965_txq_ctx_stop()
2071 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { in il4965_txq_ctx_stop()
2072 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); in il4965_txq_ctx_stop()
2078 if (ret < 0) in il4965_txq_ctx_stop()
2079 IL_ERR("Timeout stopping DMA channel %d [0x%08x]", in il4965_txq_ctx_stop()
2088 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2095 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) in il4965_txq_ctx_activate_free()
2110 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | in il4965_tx_queue_stop_scheduler()
2131 if (txq_id & 0x1) in il4965_tx_queue_set_q2ratid()
2132 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); in il4965_tx_queue_set_q2ratid()
2134 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); in il4965_tx_queue_set_q2ratid()
2138 return 0; in il4965_tx_queue_set_q2ratid()
2184 * Assumes that ssn_idx is valid (!= 0xFFF) */ in il4965_txq_agg_enable()
2185 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); in il4965_txq_agg_enable()
2186 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); in il4965_txq_agg_enable()
2210 return 0; in il4965_txq_agg_enable()
2226 if (unlikely(tx_fifo < 0)) in il4965_tx_agg_start()
2263 if (tid_data->tfds_in_queue == 0) { in il4965_tx_agg_start()
2297 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); in il4965_txq_agg_disable()
2298 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); in il4965_txq_agg_disable()
2299 /* supposes that ssn_idx is valid (!= 0xFFF) */ in il4965_txq_agg_disable()
2304 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0); in il4965_txq_agg_disable()
2306 return 0; in il4965_txq_agg_disable()
2320 if (unlikely(tx_fifo_id < 0)) in il4965_tx_agg_stop()
2361 return 0; in il4965_tx_agg_stop()
2384 return 0; in il4965_tx_agg_stop()
2412 if (tid_data->tfds_in_queue == 0) { in il4965_txq_check_empty()
2420 return 0; in il4965_txq_check_empty()
2435 atomic_dec_return(&sta_priv->pending_frames) == 0) in il4965_non_agg_tx_status()
2457 int nfreed = 0; in il4965_tx_queue_reclaim()
2461 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { in il4965_tx_queue_reclaim()
2463 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, in il4965_tx_queue_reclaim()
2465 return 0; in il4965_tx_queue_reclaim()
2501 int successes = 0; in il4965_tx_status_reply_compressed_ba()
2512 agg->wait_for_ba = 0; in il4965_tx_status_reply_compressed_ba()
2517 if (sh < 0) /* tbw something is wrong with indices */ in il4965_tx_status_reply_compressed_ba()
2518 sh += 0x100; in il4965_tx_status_reply_compressed_ba()
2534 i = 0; in il4965_tx_status_reply_compressed_ba()
2539 i, (agg->start_idx + i) & 0xff, agg->start_idx + i); in il4965_tx_status_reply_compressed_ba()
2547 memset(&info->status, 0, sizeof(info->status)); in il4965_tx_status_reply_compressed_ba()
2554 return 0; in il4965_tx_status_reply_compressed_ba()
2568 int start = 0; in il4965_find_station()
2637 return 0; in il4965_tx_status_to_mac80211()
2662 agg->bitmap = 0; in il4965_tx_status_reply_tx()
2667 status = le16_to_cpu(frame_status[0].status); in il4965_tx_status_reply_tx()
2674 info->status.rates[0].count = tx_resp->failure_frame + 1; in il4965_tx_status_reply_tx()
2679 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff, in il4965_tx_status_reply_tx()
2683 agg->wait_for_ba = 0; in il4965_tx_status_reply_tx()
2686 u64 bitmap = 0; in il4965_tx_status_reply_tx()
2691 for (i = 0; i < agg->frame_count; i++) { in il4965_tx_status_reply_tx()
2712 if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) { in il4965_tx_status_reply_tx()
2724 sh = (start - idx) + 0xff; in il4965_tx_status_reply_tx()
2726 sh = 0; in il4965_tx_status_reply_tx()
2729 sh = 0xff - (start - idx); in il4965_tx_status_reply_tx()
2730 else if (sh < 0) { in il4965_tx_status_reply_tx()
2734 sh = 0; in il4965_tx_status_reply_tx()
2737 D_TX_REPLY("start=%d bitmap=0x%llx\n", start, in il4965_tx_status_reply_tx()
2743 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", in il4965_tx_status_reply_tx()
2750 return 0; in il4965_tx_status_reply_tx()
2767 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; in il4965_hdl_tx()
2775 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { in il4965_hdl_tx()
2777 "is out of range [0-%d] %d %d\n", txq_id, idx, in il4965_hdl_tx()
2786 memset(&info->status, 0, sizeof(info->status)); in il4965_hdl_tx()
2791 tid = qc[0] & 0xf; in il4965_hdl_tx()
2828 if (txq->q.read_ptr != (scd_ssn & 0xff)) { in il4965_hdl_tx()
2829 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); in il4965_hdl_tx()
2843 info->status.rates[0].count = tx_resp->failure_frame + 1; in il4965_hdl_tx()
2849 D_TX_REPLY("TXQ %d status %s (0x%08x) " in il4965_hdl_tx()
2850 "rate_n_flags 0x%x retries %d\n", txq_id, in il4965_hdl_tx()
2880 struct ieee80211_tx_rate *r = &info->status.rates[0]; in il4965_hwrate_to_tx_control()
2944 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); in il4965_hdl_compressed_ba()
2951 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = " in il4965_hdl_compressed_ba()
2955 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx, in il4965_hdl_compressed_ba()
2964 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { in il4965_hdl_compressed_ba()
3025 u32 rate_flags = 0; in il4965_sta_alloc_lq()
3047 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) in il4965_sta_alloc_lq()
3088 ret = il_add_station_common(il, addr, 0, NULL, &sta_id); in il4965_add_bssid_station()
3117 return 0; in il4965_add_bssid_station()
3137 memset(wep_cmd, 0, in il4965_static_wepkey_cmd()
3140 for (i = 0; i < WEP_KEYS_MAX; i++) { in il4965_static_wepkey_cmd()
3163 return 0; in il4965_static_wepkey_cmd()
3185 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key)); in il4965_remove_default_wep_key()
3189 return 0; in il4965_remove_default_wep_key()
3230 __le16 key_flags = 0; in il4965_set_wep_dynamic_key_info()
3284 __le16 key_flags = 0; in il4965_set_ccmp_dynamic_key_info()
3332 __le16 key_flags = 0; in il4965_set_tkip_dynamic_key_info()
3368 return 0; in il4965_set_tkip_dynamic_key_info()
3393 for (i = 0; i < 5; i++) in il4965_update_tkip_key()
3420 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3; in il4965_remove_dynamic_key()
3431 return 0; in il4965_remove_dynamic_key()
3435 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx, in il4965_remove_dynamic_key()
3438 return 0; in il4965_remove_dynamic_key()
3445 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key)); in il4965_remove_dynamic_key()
3446 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo)); in il4965_remove_dynamic_key()
3457 return 0; in il4965_remove_dynamic_key()
3540 return 0; in il4965_alloc_bcast_station()
3570 return 0; in il4965_update_bcast_station()
3617 il->stations[sta_id].sta.station_flags_msk = 0; in il4965_sta_rx_agg_start()
3645 il->stations[sta_id].sta.station_flags_msk = 0; in il4965_sta_rx_agg_stop()
3700 il->frames_count = 0; in il4965_clear_free_frames()
3728 memset(frame, 0, sizeof(*frame)); in il4965_free_frame()
3739 return 0; in il4965_fill_beacon_frame()
3742 return 0; in il4965_fill_beacon_frame()
3793 return 0; in il4965_hw_get_beacon_cmd()
3798 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); in il4965_hw_get_beacon_cmd()
3805 return 0; in il4965_hw_get_beacon_cmd()
3807 return 0; in il4965_hw_get_beacon_cmd()
3853 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]); in il4965_send_beacon_cmd()
3868 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << in il4965_tfd_tb_get_addr()
3890 hi_n_len |= ((addr >> 16) >> 16) & 0xF; in il4965_tfd_set_tb()
3900 return tfd->num_tbs & 0x1f; in il4965_tfd_get_num_tbs()
3967 memset(tfd, 0, sizeof(*tfd)); in il4965_hw_txq_attach_buf_to_tfd()
3984 return 0; in il4965_hw_txq_attach_buf_to_tfd()
4002 return 0; in il4965_hw_tx_queue_init()
4019 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n", in il4965_hdl_alive()
4076 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n", in il4965_hdl_beacon()
4213 u8 fill_rx = 0; in il4965_rx_handle()
4219 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; in il4965_rx_handle()
4228 if (total_empty < 0) in il4965_rx_handle()
4260 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i, in il4965_rx_handle()
4266 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r, in il4965_rx_handle()
4293 pci_map_page(il->pci_dev, rxb->page, 0, in il4965_rx_handle()
4319 count = 0; in il4965_rx_handle()
4345 u32 inta, handled = 0; in il4965_irq_tasklet()
4371 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, in il4965_irq_tasklet()
4422 int hw_rf_kill = 0; in il4965_irq_tasklet()
4457 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n", in il4965_irq_tasklet()
4472 for (i = 0; i < il->hw_params.max_txq_num; i++) in il4965_irq_tasklet()
4498 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); in il4965_irq_tasklet()
4503 IL_WARN("Disabled INTA bits 0x%08x were pending\n", in il4965_irq_tasklet()
4505 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh); in il4965_irq_tasklet()
4521 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " in il4965_irq_tasklet()
4522 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); in il4965_irq_tasklet()
4551 return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); in il4965_show_debug_level()
4562 ret = kstrtoul(buf, 0, &val); in il4965_store_debug_level()
4615 IL_ERR("failed setting tx power (0x%08x).\n", ret); in il4965_store_tx_power()
4660 _il_wr(il, CSR_RESET, 0); in il4965_nic_start()
4713 case 0: in il4965_load_firmware()
4751 return 0; in il4965_load_firmware()
4774 memset(&pieces, 0, sizeof(pieces)); in il4965_ucode_callback()
4833 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver); in il4965_ucode_callback()
4921 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", in il4965_ucode_callback()
5036 "NMI_INTERRUPT_WDG", 0x34}, {
5037 "SYSASSERT", 0x35}, {
5038 "UCODE_VERSION_MISMATCH", 0x37}, {
5039 "BAD_COMMAND", 0x38}, {
5040 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5041 "FATAL_ERROR", 0x3D}, {
5042 "NMI_TRM_HW_ERR", 0x46}, {
5043 "NMI_INTERRUPT_TRM", 0x4C}, {
5044 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5045 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5046 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5047 "NMI_INTERRUPT_HOST", 0x66}, {
5048 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5049 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5050 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5051 "ADVANCED_SYSASSERT", 0},};
5063 for (i = 0; i < max; i++) { in il4965_desc_lookup()
5087 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n", in il4965_dump_nic_error_log()
5096 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count); in il4965_dump_nic_error_log()
5114 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", in il4965_dump_nic_error_log()
5117 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1, in il4965_dump_nic_error_log()
5126 int ret = 0; in il4965_rf_kill_ct_config()
5171 il_write_targ_mem(il, a, 0); in il4965_alive_notify()
5173 il_write_targ_mem(il, a, 0); in il4965_alive_notify()
5179 il_write_targ_mem(il, a, 0); in il4965_alive_notify()
5185 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++) in il4965_alive_notify()
5196 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); in il4965_alive_notify()
5199 for (i = 0; i < il->hw_params.max_txq_num; i++) { in il4965_alive_notify()
5202 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0); in il4965_alive_notify()
5203 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); in il4965_alive_notify()
5227 il4965_txq_set_sched(il, IL_MASK(0, 6)); in il4965_alive_notify()
5229 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0); in il4965_alive_notify()
5232 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped)); in il4965_alive_notify()
5233 for (i = 0; i < 4; i++) in il4965_alive_notify()
5234 atomic_set(&il->queue_stop_count[i], 0); in il4965_alive_notify()
5236 /* reset to 0 to enable all the queue first */ in il4965_alive_notify()
5237 il->txq_ctx_active_msk = 0; in il4965_alive_notify()
5241 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { in il4965_alive_notify()
5249 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0); in il4965_alive_notify()
5254 return 0; in il4965_alive_notify()
5265 int ret = 0; in il4965_alive_start()
5373 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys)); in __il4965_down()
5374 il->_4965.key_mapping_keys = 0; in __il4965_down()
5440 memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); in __il4965_down()
5473 if (ret >= 0) in il4965_set_hw_ready()
5544 return 0; in __il4965_up()
5547 _il_wr(il, CSR_INT, 0xFFFFFFFF); in __il4965_up()
5564 _il_wr(il, CSR_INT, 0xFFFFFFFF); in __il4965_up()
5577 for (i = 0; i < MAX_HW_RESTARTS; i++) { in __il4965_up()
5594 return 0; in __il4965_up()
5675 il->is_open = 0; in il4965_bg_restart()
5784 return 0; in il4965_mac_setup_register()
5826 return 0; in il4965_mac_start()
5839 il->is_open = 0; in il4965_mac_stop()
5847 _il_wr(il, CSR_INT, 0xFFFFFFFF); in il4965_mac_stop()
5862 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, in il4965_mac_tx()
5988 ret = 0; in il4965_mac_ampdu_action()
6000 ret = 0; in il4965_mac_ampdu_action()
6003 ret = 0; in il4965_mac_ampdu_action()
6026 atomic_set(&sta_priv->pending_frames, 0); in il4965_mac_sta_add()
6044 return 0; in il4965_mac_sta_add()
6108 il->staging.flags = 0; in il4965_mac_channel_switch()
6125 il->switch_channel = 0; in il4965_mac_channel_switch()
6139 __le32 filter_or = 0, filter_nand = 0; in il4965_configure_filter()
6146 } while (0) in il4965_configure_filter()
6148 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags, in il4965_configure_filter()
6232 timer_setup(&il->stats_periodic, il4965_bg_stats_periodic, 0); in il4965_setup_deferred_work()
6234 timer_setup(&il->watchdog, il_bg_watchdog, 0); in il4965_setup_deferred_work()
6257 for (i = 0; i < RATE_COUNT_LEGACY; i++) { in il4965_init_hw_rates()
6261 rates[i].flags = 0; in il4965_init_hw_rates()
6268 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE; in il4965_init_hw_rates()
6279 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8)); in il4965_set_wr_ptrs()
6290 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0; in il4965_tx_queue_set_status()
6371 return 0; in il4965_init_drv()
6393 D_INFO("HW Revision ID = 0x%X\n", il->rev_id); in il4965_hw_detect()
6398 .max_nrg_cck = 0, /* not used, set to 0 */
6474 int err = 0; in il4965_pci_probe()
6541 il->hw_base = pci_ioremap_bar(pdev, 0); in il4965_pci_probe()
6547 D_INFO("pci_resource_len = 0x%08llx\n", in il4965_pci_probe()
6548 (unsigned long long)pci_resource_len(pdev, 0)); in il4965_pci_probe()
6565 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev); in il4965_pci_probe()
6567 /* We disable the RETRY_TIMEOUT register (0x41) to keep in il4965_pci_probe()
6569 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); in il4965_pci_probe()
6592 il4965_eeprom_get_mac(il, il->addresses[0].addr); in il4965_pci_probe()
6593 D_INFO("MAC address: %pM\n", il->addresses[0].addr); in il4965_pci_probe()
6659 return 0; in il4965_pci_probe()
6708 il->mac80211_registered = 0; in il4965_pci_remove()
6779 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6780 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
6781 {0}
6836 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
6842 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size (default 0 [disabled])");