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Searched refs:ucClockSelect (Results 1 – 9 of 9) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c1234 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1238 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1242 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1247 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1252 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c1234 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1238 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1242 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1247 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1252 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c1191 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1195 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1199 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1204 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1208 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1211 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c1207 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1212 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1216 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1220 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1224 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1227 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c1113 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1119 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1131 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1143 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1155 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c1113 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1119 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1131 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1143 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1155 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c1113 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1119 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1131 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1143 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1155 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c1113 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1119 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1131 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1143 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1155 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c1113 MS_U8 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect() local
1119 ucClockSelect = MHL_DVI_PORT_A; in _mhal_mhl_CbusAndClockSelect()
1131 ucClockSelect = MHL_DVI_PORT_B; in _mhal_mhl_CbusAndClockSelect()
1143 ucClockSelect = MHL_DVI_PORT_C; in _mhal_mhl_CbusAndClockSelect()
1155 ucClockSelect = MHL_DVI_PORT_D; in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()