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Searched refs:clock (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/usb/drv/usb_ecos/usbhost/
H A DdrvEHCI_SCHD.cxx1117 U32 frame, clock, now_uframe, mod; in scan_periodic() local
1129 clock = now_uframe >> 3; in scan_periodic()
1138 if (frame == clock) in scan_periodic()
1245 if (frame == clock) { in scan_periodic()
1259 clock = now_uframe >> 3; in scan_periodic()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_pip.c.0719 // Enable sub window clock
724 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED); // Enable clock
728 … MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_GATED); // Enable clock
740 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
744 … MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_GATED); // Enable clock
H A Dmvideo.c.0481 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
491 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, ENABLE, CKG_FICLK_F2_GATED); // Enable clock
494 … MDrv_WriteRegBit(REG_CKG_FCLK, ENABLE, CKG_FCLK_GATED); // Enable clock
497 … MDrv_WriteRegBit(REG_CKG_IDCLK2, ENABLE, CKG_IDCLK2_GATED); // Enable clock
505 …iteRegBit(REG_CKG_SC1_FECLK_F2, ENABLE, CKG_SC1_FECLK_F2_GATED); // Enable clock
508 …iteRegBit(REG_CKG_SC1_FCLK, ENABLE, CKG_SC1_FCLK_GATED); // Enable clock
511 …iteRegBit(REG_CKG_SC1_IDCLK2, ENABLE, CKG_SC1_IDCLK2_GATED); // Enable clock
524 … MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED); // Enable clock
539 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, ENABLE, CKG_FICLK_F2_GATED); // Enable clock
542 … MDrv_WriteRegBit(REG_CKG_FCLK, ENABLE, CKG_FCLK_GATED); // Enable clock
[all …]
/utopia/UTPA2-700.0.x/modules/flash/drv/flash/serial/
H A DRelease Note.txt25 2010-01-04: [T2,3,4,7,8,9; Janus] Added new flash chip, FLASH_IC_S25FL008A (size 1MB with clock 50M…
30 2) Add new function to change SPI clock div
/utopia/UTPA2-700.0.x/projects/tools/lint/mips-linux-gnu_include/rpcsvc/
H A Dspray.x53 spraytimeval clock; member
H A Dspray.h26 spraytimeval clock; member
/utopia/UTPA2-700.0.x/projects/tools/lint/mips-linux-gnu_include/linux/
H A Dscc.h152 long clock; /* clock */ member
/utopia/UTPA2-700.0.x/projects/tools/lint/mips-linux-gnu_include/
H A Dtime.h184 extern clock_t clock (void) __THROW;
/utopia/UTPA2-700.0.x/projects/tools/lint/aeon_include/
H A Dtime.h46 clock_t _EXFUN(clock, (void));
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h.0703 #define REG_CKG_ODCLK (REG_CHIPTOP_BASE + 0xA6 ) // output dot clock
825 #define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock
/utopia/UTPA2-700.0.x/modules/mfe/drv/mfe_ex/cModel/
H A Dmfe_reg_jpge.c_186 mfe_reg->reg16 = 0xffff; // clock gating
/utopia/UTPA2-700.0.x/projects/build/Ksym/
H A D.Ksym.o.cmd293 $(wildcard include/config/mp/static/timer/clock/source.h) \
294 $(wildcard include/config/mp/static/timer/clock/source/debug.h) \
/utopia/UTPA2-700.0.x/projects/build/
H A Dnvr_msr620q_config_nand-jinyan1842 # PTP clock support
/utopia/UTPA2-700.0.x/modules/audio/api/audio/
H A DapiAUDIO_v2_customer.c1899 dtsUint32 clock; member
14026 memcpy(&pFileInfo->timecode.clock, timeChunk, 4); in AU_CUS_DTS_Parser_dtsDecodeTIMECODE()
14027 … pFileInfo->timecode.clock = AU_CUS_DTS_Parser_dtsHDEndianConvert32(pFileInfo->timecode.clock); in AU_CUS_DTS_Parser_dtsDecodeTIMECODE()