xref: /utopia/UTPA2-700.0.x/projects/tools/lint/mips-linux-gnu_include/linux/scc.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi /* $Id: scc.h,v 1.29 1997/04/02 14:56:45 jreuter Exp jreuter $ */
2*53ee8cc1Swenshuai.xi 
3*53ee8cc1Swenshuai.xi #ifndef	_SCC_H
4*53ee8cc1Swenshuai.xi #define	_SCC_H
5*53ee8cc1Swenshuai.xi 
6*53ee8cc1Swenshuai.xi 
7*53ee8cc1Swenshuai.xi /* selection of hardware types */
8*53ee8cc1Swenshuai.xi 
9*53ee8cc1Swenshuai.xi #define PA0HZP		0x00	/* hardware type for PA0HZP SCC card and compatible */
10*53ee8cc1Swenshuai.xi #define EAGLE		0x01    /* hardware type for EAGLE card */
11*53ee8cc1Swenshuai.xi #define PC100		0x02	/* hardware type for PC100 card */
12*53ee8cc1Swenshuai.xi #define PRIMUS		0x04	/* hardware type for PRIMUS-PC (DG9BL) card */
13*53ee8cc1Swenshuai.xi #define DRSI		0x08	/* hardware type for DRSI PC*Packet card */
14*53ee8cc1Swenshuai.xi #define BAYCOM		0x10	/* hardware type for BayCom (U)SCC */
15*53ee8cc1Swenshuai.xi 
16*53ee8cc1Swenshuai.xi /* DEV ioctl() commands */
17*53ee8cc1Swenshuai.xi 
18*53ee8cc1Swenshuai.xi enum SCC_ioctl_cmds {
19*53ee8cc1Swenshuai.xi 	SIOCSCCRESERVED = SIOCDEVPRIVATE,
20*53ee8cc1Swenshuai.xi 	SIOCSCCCFG,
21*53ee8cc1Swenshuai.xi 	SIOCSCCINI,
22*53ee8cc1Swenshuai.xi 	SIOCSCCCHANINI,
23*53ee8cc1Swenshuai.xi 	SIOCSCCSMEM,
24*53ee8cc1Swenshuai.xi 	SIOCSCCGKISS,
25*53ee8cc1Swenshuai.xi 	SIOCSCCSKISS,
26*53ee8cc1Swenshuai.xi 	SIOCSCCGSTAT,
27*53ee8cc1Swenshuai.xi 	SIOCSCCCAL
28*53ee8cc1Swenshuai.xi };
29*53ee8cc1Swenshuai.xi 
30*53ee8cc1Swenshuai.xi /* Device parameter control (from WAMPES) */
31*53ee8cc1Swenshuai.xi 
32*53ee8cc1Swenshuai.xi enum L1_params {
33*53ee8cc1Swenshuai.xi 	PARAM_DATA,
34*53ee8cc1Swenshuai.xi 	PARAM_TXDELAY,
35*53ee8cc1Swenshuai.xi 	PARAM_PERSIST,
36*53ee8cc1Swenshuai.xi 	PARAM_SLOTTIME,
37*53ee8cc1Swenshuai.xi 	PARAM_TXTAIL,
38*53ee8cc1Swenshuai.xi 	PARAM_FULLDUP,
39*53ee8cc1Swenshuai.xi 	PARAM_SOFTDCD,		/* was: PARAM_HW */
40*53ee8cc1Swenshuai.xi 	PARAM_MUTE,		/* ??? */
41*53ee8cc1Swenshuai.xi 	PARAM_DTR,
42*53ee8cc1Swenshuai.xi 	PARAM_RTS,
43*53ee8cc1Swenshuai.xi 	PARAM_SPEED,
44*53ee8cc1Swenshuai.xi 	PARAM_ENDDELAY,		/* ??? */
45*53ee8cc1Swenshuai.xi 	PARAM_GROUP,
46*53ee8cc1Swenshuai.xi 	PARAM_IDLE,
47*53ee8cc1Swenshuai.xi 	PARAM_MIN,
48*53ee8cc1Swenshuai.xi 	PARAM_MAXKEY,
49*53ee8cc1Swenshuai.xi 	PARAM_WAIT,
50*53ee8cc1Swenshuai.xi 	PARAM_MAXDEFER,
51*53ee8cc1Swenshuai.xi 	PARAM_TX,
52*53ee8cc1Swenshuai.xi 	PARAM_HWEVENT = 31,
53*53ee8cc1Swenshuai.xi 	PARAM_RETURN = 255	/* reset kiss mode */
54*53ee8cc1Swenshuai.xi };
55*53ee8cc1Swenshuai.xi 
56*53ee8cc1Swenshuai.xi /* fulldup parameter */
57*53ee8cc1Swenshuai.xi 
58*53ee8cc1Swenshuai.xi enum FULLDUP_modes {
59*53ee8cc1Swenshuai.xi 	KISS_DUPLEX_HALF,	/* normal CSMA operation */
60*53ee8cc1Swenshuai.xi 	KISS_DUPLEX_FULL,	/* fullduplex, key down trx after transmission */
61*53ee8cc1Swenshuai.xi 	KISS_DUPLEX_LINK,	/* fullduplex, key down trx after 'idletime' sec */
62*53ee8cc1Swenshuai.xi 	KISS_DUPLEX_OPTIMA	/* fullduplex, let the protocol layer control the hw */
63*53ee8cc1Swenshuai.xi };
64*53ee8cc1Swenshuai.xi 
65*53ee8cc1Swenshuai.xi /* misc. parameters */
66*53ee8cc1Swenshuai.xi 
67*53ee8cc1Swenshuai.xi #define TIMER_OFF	65535U	/* to switch off timers */
68*53ee8cc1Swenshuai.xi #define NO_SUCH_PARAM	65534U	/* param not implemented */
69*53ee8cc1Swenshuai.xi 
70*53ee8cc1Swenshuai.xi /* HWEVENT parameter */
71*53ee8cc1Swenshuai.xi 
72*53ee8cc1Swenshuai.xi enum HWEVENT_opts {
73*53ee8cc1Swenshuai.xi 	HWEV_DCD_ON,
74*53ee8cc1Swenshuai.xi 	HWEV_DCD_OFF,
75*53ee8cc1Swenshuai.xi 	HWEV_ALL_SENT
76*53ee8cc1Swenshuai.xi };
77*53ee8cc1Swenshuai.xi 
78*53ee8cc1Swenshuai.xi /* channel grouping */
79*53ee8cc1Swenshuai.xi 
80*53ee8cc1Swenshuai.xi #define RXGROUP		0100	/* if set, only tx when all channels clear */
81*53ee8cc1Swenshuai.xi #define TXGROUP		0200	/* if set, don't transmit simultaneously */
82*53ee8cc1Swenshuai.xi 
83*53ee8cc1Swenshuai.xi /* Tx/Rx clock sources */
84*53ee8cc1Swenshuai.xi 
85*53ee8cc1Swenshuai.xi enum CLOCK_sources {
86*53ee8cc1Swenshuai.xi 	CLK_DPLL,	/* normal halfduplex operation */
87*53ee8cc1Swenshuai.xi 	CLK_EXTERNAL,	/* external clocking (G3RUH/DF9IC modems) */
88*53ee8cc1Swenshuai.xi 	CLK_DIVIDER,	/* Rx = DPLL, Tx = divider (fullduplex with */
89*53ee8cc1Swenshuai.xi 			/* modems without clock regeneration */
90*53ee8cc1Swenshuai.xi 	CLK_BRG		/* experimental fullduplex mode with DPLL/BRG for */
91*53ee8cc1Swenshuai.xi 			/* MODEMs without clock recovery */
92*53ee8cc1Swenshuai.xi };
93*53ee8cc1Swenshuai.xi 
94*53ee8cc1Swenshuai.xi /* Tx state */
95*53ee8cc1Swenshuai.xi 
96*53ee8cc1Swenshuai.xi enum TX_state {
97*53ee8cc1Swenshuai.xi 	TXS_IDLE,	/* Transmitter off, no data pending */
98*53ee8cc1Swenshuai.xi 	TXS_BUSY,	/* waiting for permission to send / tailtime */
99*53ee8cc1Swenshuai.xi 	TXS_ACTIVE,	/* Transmitter on, sending data */
100*53ee8cc1Swenshuai.xi 	TXS_NEWFRAME,	/* reset CRC and send (next) frame */
101*53ee8cc1Swenshuai.xi 	TXS_IDLE2,	/* Transmitter on, no data pending */
102*53ee8cc1Swenshuai.xi 	TXS_WAIT,	/* Waiting for Mintime to expire */
103*53ee8cc1Swenshuai.xi 	TXS_TIMEOUT	/* We had a transmission timeout */
104*53ee8cc1Swenshuai.xi };
105*53ee8cc1Swenshuai.xi 
106*53ee8cc1Swenshuai.xi typedef unsigned long io_port;	/* type definition for an 'io port address' */
107*53ee8cc1Swenshuai.xi 
108*53ee8cc1Swenshuai.xi /* SCC statistical information */
109*53ee8cc1Swenshuai.xi 
110*53ee8cc1Swenshuai.xi struct scc_stat {
111*53ee8cc1Swenshuai.xi         long rxints;            /* Receiver interrupts */
112*53ee8cc1Swenshuai.xi         long txints;            /* Transmitter interrupts */
113*53ee8cc1Swenshuai.xi         long exints;            /* External/status interrupts */
114*53ee8cc1Swenshuai.xi         long spints;            /* Special receiver interrupts */
115*53ee8cc1Swenshuai.xi 
116*53ee8cc1Swenshuai.xi         long txframes;          /* Packets sent */
117*53ee8cc1Swenshuai.xi         long rxframes;          /* Number of Frames Actually Received */
118*53ee8cc1Swenshuai.xi         long rxerrs;            /* CRC Errors */
119*53ee8cc1Swenshuai.xi         long txerrs;		/* KISS errors */
120*53ee8cc1Swenshuai.xi 
121*53ee8cc1Swenshuai.xi 	unsigned int nospace;	/* "Out of buffers" */
122*53ee8cc1Swenshuai.xi 	unsigned int rx_over;	/* Receiver Overruns */
123*53ee8cc1Swenshuai.xi 	unsigned int tx_under;	/* Transmitter Underruns */
124*53ee8cc1Swenshuai.xi 
125*53ee8cc1Swenshuai.xi 	unsigned int tx_state;	/* Transmitter state */
126*53ee8cc1Swenshuai.xi 	int tx_queued;		/* tx frames enqueued */
127*53ee8cc1Swenshuai.xi 
128*53ee8cc1Swenshuai.xi 	unsigned int maxqueue;	/* allocated tx_buffers */
129*53ee8cc1Swenshuai.xi 	unsigned int bufsize;	/* used buffersize */
130*53ee8cc1Swenshuai.xi };
131*53ee8cc1Swenshuai.xi 
132*53ee8cc1Swenshuai.xi struct scc_modem {
133*53ee8cc1Swenshuai.xi 	long speed;		/* Line speed, bps */
134*53ee8cc1Swenshuai.xi 	char clocksrc;		/* 0 = DPLL, 1 = external, 2 = divider */
135*53ee8cc1Swenshuai.xi 	char nrz;		/* NRZ instead of NRZI */
136*53ee8cc1Swenshuai.xi };
137*53ee8cc1Swenshuai.xi 
138*53ee8cc1Swenshuai.xi struct scc_kiss_cmd {
139*53ee8cc1Swenshuai.xi 	int  	 command;	/* one of the KISS-Commands defined above */
140*53ee8cc1Swenshuai.xi 	unsigned param;		/* KISS-Param */
141*53ee8cc1Swenshuai.xi };
142*53ee8cc1Swenshuai.xi 
143*53ee8cc1Swenshuai.xi struct scc_hw_config {
144*53ee8cc1Swenshuai.xi 	io_port data_a;		/* data port channel A */
145*53ee8cc1Swenshuai.xi 	io_port ctrl_a;		/* control port channel A */
146*53ee8cc1Swenshuai.xi 	io_port data_b;		/* data port channel B */
147*53ee8cc1Swenshuai.xi 	io_port ctrl_b;		/* control port channel B */
148*53ee8cc1Swenshuai.xi 	io_port vector_latch;	/* INTACK-Latch (#) */
149*53ee8cc1Swenshuai.xi 	io_port	special;	/* special function port */
150*53ee8cc1Swenshuai.xi 
151*53ee8cc1Swenshuai.xi 	int	irq;		/* irq */
152*53ee8cc1Swenshuai.xi 	long	clock;		/* clock */
153*53ee8cc1Swenshuai.xi 	char	option;		/* command for function port */
154*53ee8cc1Swenshuai.xi 
155*53ee8cc1Swenshuai.xi 	char brand;		/* hardware type */
156*53ee8cc1Swenshuai.xi 	char escc;		/* use ext. features of a 8580/85180/85280 */
157*53ee8cc1Swenshuai.xi };
158*53ee8cc1Swenshuai.xi 
159*53ee8cc1Swenshuai.xi /* (#) only one INTACK latch allowed. */
160*53ee8cc1Swenshuai.xi 
161*53ee8cc1Swenshuai.xi 
162*53ee8cc1Swenshuai.xi struct scc_mem_config {
163*53ee8cc1Swenshuai.xi 	unsigned int dummy;
164*53ee8cc1Swenshuai.xi 	unsigned int bufsize;
165*53ee8cc1Swenshuai.xi };
166*53ee8cc1Swenshuai.xi 
167*53ee8cc1Swenshuai.xi struct scc_calibrate {
168*53ee8cc1Swenshuai.xi 	unsigned int time;
169*53ee8cc1Swenshuai.xi 	unsigned char pattern;
170*53ee8cc1Swenshuai.xi };
171*53ee8cc1Swenshuai.xi 
172*53ee8cc1Swenshuai.xi #endif /* defined(_SCC_H) */
173