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Searched refs:bEnMask (Results 1 – 25 of 66) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/mainz/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/messi/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/mvd/
H A DhalMVD.c472 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
474 HAL_VPU_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
478 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
479 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
483 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
484 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
H A DhalMVD.h294 void HAL_MVD_SetReqMask(MS_BOOL bEnMask);
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/mvd_lite/
H A DhalMVD_EX.c1062 void HAL_MVD_SetReqMask(MS_U32 u32Id, MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
1064 HAL_VPU_EX_MIU_RW_Protect(u32Id, bEnMask); in HAL_MVD_SetReqMask()
1068 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT6); //MVD R/W in HAL_MVD_SetReqMask()
1069 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT2); //MVD bbu R/W in HAL_MVD_SetReqMask()
1070 HAL_MVD_RegWriteBit(MIU1_RQ4_MASK_H, bEnMask, BIT1); //RTO in HAL_MVD_SetReqMask()
1074 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT6); //MVD R/W in HAL_MVD_SetReqMask()
1075 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT2); //MVD bbu R/W in HAL_MVD_SetReqMask()
1076 HAL_MVD_RegWriteBit(MIU0_RQ4_MASK_H, bEnMask, BIT1); //RTO in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/mvd_v3/
H A DhalMVD_EX.c1064 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
1066 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
1070 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1071 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
1075 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1076 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
1080 HAL_MVD_RegWriteBit(MIU2_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1081 HAL_MVD_RegWriteBit(MIU2_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/mvd_v3/
H A DhalMVD_EX.c1064 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
1066 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
1070 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1071 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
1075 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1076 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
1080 HAL_MVD_RegWriteBit(MIU2_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1081 HAL_MVD_RegWriteBit(MIU2_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/mvd_v3/
H A DhalMVD_EX.c1041 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
1043 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
1047 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1048 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
1049 HAL_MVD_RegWriteBit(MIU1_RQ4_MASK_L, bEnMask, BIT6); //MVD TLB Mheg Codec in HAL_MVD_SetReqMask()
1053 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
1054 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
1055 HAL_MVD_RegWriteBit(MIU0_RQ4_MASK_L, bEnMask, BIT6); //MVD TLB Mheg Codec in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/mvd_ex/
H A DhalMVD_EX.c947 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
949 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
953 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
954 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
958 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
959 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/mvd_ex/
H A DhalMVD_EX.c913 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
915 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
919 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
920 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
924 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
925 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/mvd_ex/
H A DhalMVD_EX.c947 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
949 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
953 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
954 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
958 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
959 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/mvd_ex/
H A DhalMVD_EX.c913 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
915 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
919 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
920 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
924 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
925 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/mvd_ex/
H A DhalMVD_EX.c913 void HAL_MVD_SetReqMask(MS_BOOL bEnMask) in HAL_MVD_SetReqMask() argument
915 HAL_VPU_EX_MIU_RW_Protect(bEnMask); in HAL_MVD_SetReqMask()
919 HAL_MVD_RegWriteBit(MIU1_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
920 HAL_MVD_RegWriteBit(MIU1_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()
924 HAL_MVD_RegWriteBit(MIU0_RQ2_MASK_L, bEnMask, BIT4); //MVD R/W in HAL_MVD_SetReqMask()
925 HAL_MVD_RegWriteBit(MIU0_RQ0_MASK_H, bEnMask, BIT4); //MVD bbu R/W in HAL_MVD_SetReqMask()

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