Searched refs:_RegOtherCtrl (Results 1 – 1 of 1) sorted by relevance
56 static REG_OTHER_Ctrl *_RegOtherCtrl = NULL; // Other/resample variable196 …_RegOtherCtrl = (REG_OTHER_Ctrl*) (u32BankAddr + 0xE0400UL); // Other … in HAL_TSP_SetBank()274 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()329 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_FIX_PINPON_SYNCP_IN); in HAL_TSP_HwPatch()370 REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_CPU_LOAD_CODE_ONLY_ONE_TIME_BY_TEE); in HAL_TSP_HwPatch()373 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, CFG_OTHER_75_REG_FIXED_MIU_REQ_FLUSH); in HAL_TSP_HwPatch()378 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE); in HAL_TSP_HwPatch()544 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()547 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE) in HAL_TSP_Power()552 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE); in HAL_TSP_Power()[all …]