Lines Matching refs:_RegOtherCtrl
56 static REG_OTHER_Ctrl *_RegOtherCtrl = NULL; // Other/resample variable
196 …_RegOtherCtrl = (REG_OTHER_Ctrl*) (u32BankAddr + 0xE0400UL); // Other … in HAL_TSP_SetBank()
274 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
329 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_FIX_PINPON_SYNCP_IN); in HAL_TSP_HwPatch()
370 REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_CPU_LOAD_CODE_ONLY_ONE_TIME_BY_TEE); in HAL_TSP_HwPatch()
373 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, CFG_OTHER_75_REG_FIXED_MIU_REQ_FLUSH); in HAL_TSP_HwPatch()
378 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE); in HAL_TSP_HwPatch()
544 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
547 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE) in HAL_TSP_Power()
552 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE); in HAL_TSP_Power()
1242 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, (CFG_OTHER_13_REG_3WIRE_SERIAL_MODE_EN << tsIf)); in HAL_TSP_TSIF_3Wire()
1246 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_13, (CFG_OTHER_13_REG_3WIRE_SERIAL_MODE_EN << tsIf)); in HAL_TSP_TSIF_3Wire()
1404 … REG16_SET(&_RegOtherCtrl->CFG_OTHER_19, (CFG_OTHER_19_REG_FILEIN0_DMAR_PROTECT_EN << eFileEng)); in HAL_TSP_FILEIN_Address_Protect_En()
1408 … REG16_CLR(&_RegOtherCtrl->CFG_OTHER_19, (CFG_OTHER_19_REG_FILEIN0_DMAR_PROTECT_EN << eFileEng)); in HAL_TSP_FILEIN_Address_Protect_En()
3212 …REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_70, CFG_OTHER_70_REG_VQ_WR_THRESHOLD_MASK, (0x8 << CFG_OTHER… in _HAL_TSP_VQ_TxConfig()
3213 …REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_70, CFG_OTHER_70_REG_VQ_FORCEFIRE_CNT_1K_MASK, (0xC << CFG_O… in _HAL_TSP_VQ_TxConfig()
3258 REG32_W(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3259 REG16_W(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_size_208byte, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
3286 REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_RESET); in HAL_TSP_VQ_Reset()
3290 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_RESET); in HAL_TSP_VQ_Reset()
3306 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, (CFG_OTHER_75_REG_VQ_TX_BLOCK_DISABLE << vqId)); in HAL_TSP_VQ_Block_Dis()
3310 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_75, (CFG_OTHER_75_REG_VQ_TX_BLOCK_DISABLE << vqId)); in HAL_TSP_VQ_Block_Dis()
3326 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_OVERFLOW_INT_E… in HAL_TSP_VQ_OverflowInt_En()
3330 …REG16_CLR(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_OVERFLOW_INT_E… in HAL_TSP_VQ_OverflowInt_En()
3342 …REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_CLR_OVERFLOW_I… in HAL_TSP_VQ_OverflowInt_Clr()
3343 …REG16_CLR(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_CLR_OVERFLOW_I… in HAL_TSP_VQ_OverflowInt_Clr()
4475 …REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_1F, CFG_OTHER_1F_REG_SRC_AES_FILEIN_KEY_MASK, (tsIf << CFG_O… in HAL_TSP_FileIn_SPDConfig()
4476 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[0], 0x0000); //file-in SPD key in HAL_TSP_FileIn_SPDConfig()
4477 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[1], 0x0000); in HAL_TSP_FileIn_SPDConfig()
4478 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[2], 0x0000); in HAL_TSP_FileIn_SPDConfig()
4479 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[3], 0x0000); in HAL_TSP_FileIn_SPDConfig()
4480 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[4], 0x1111); in HAL_TSP_FileIn_SPDConfig()
4481 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[5], 0x1111); in HAL_TSP_FileIn_SPDConfig()
4482 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[6], 0x1111); in HAL_TSP_FileIn_SPDConfig()
4483 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[7], 0x1111); in HAL_TSP_FileIn_SPDConfig()
4835 … REG16_SET(&_RegOtherCtrl->CFG_OTHER_18, (CFG_OTHER_18_REG_MMFI0_DMAR_PROTECT_EN << u32MMFIEng)); in HAL_TSP_MMFI_Address_Protect_En()
4839 … REG16_CLR(&_RegOtherCtrl->CFG_OTHER_18, (CFG_OTHER_18_REG_MMFI0_DMAR_PROTECT_EN << u32MMFIEng)); in HAL_TSP_MMFI_Address_Protect_En()
4974 …REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_1F, CFG_OTHER_1F_REG_SRC_AES_PVR_KEY_MASK, ((MS_U16)u32PVREn… in HAL_TSP_PVR_SPSConfig()
4975 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[0], 0x0000); in HAL_TSP_PVR_SPSConfig()
4976 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[1], 0x0000); in HAL_TSP_PVR_SPSConfig()
4977 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[2], 0x0000); in HAL_TSP_PVR_SPSConfig()
4978 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[3], 0x0000); in HAL_TSP_PVR_SPSConfig()
4979 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[4], 0x1111); in HAL_TSP_PVR_SPSConfig()
4980 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[5], 0x1111); in HAL_TSP_PVR_SPSConfig()
4981 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[6], 0x1111); in HAL_TSP_PVR_SPSConfig()
4982 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[7], 0x1111); in HAL_TSP_PVR_SPSConfig()