| /utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/ |
| H A D | halMVOP.c | 1033 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1347 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_SetOutputTiming()
2826 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2833 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3179 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, ENABLE, VOP_HK_MASK); //default hsk mode bk background in HAL_MVOP_ResetReg()
3190 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3255 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3299 … HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), ENABLE, VOP_HK_MASK); //default hsk mode bk background in HAL_MVOP_ResetReg()
3326 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3361 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/ |
| H A D | halMVOP.c | 1028 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1082 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1408 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_SetOutputTiming()
2854 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2861 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3100 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3154 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3208 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3261 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3313 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/ |
| H A D | halMVOP.c | 1024 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1114 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2855 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2862 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3212 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, ENABLE, VOP_HK_MASK); //default hsk mode bk background in HAL_MVOP_ResetReg()
3223 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3313 … HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), ENABLE, VOP_HK_MASK); //default hsk mode bk background in HAL_MVOP_ResetReg()
3340 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3409 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3428 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/ |
| H A D | halMVOP.c | 1015 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1105 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2815 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2822 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3168 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, ENABLE, VOP_HK_MASK); //default hsk mode bk background in HAL_MVOP_ResetReg()
3179 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3264 … HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), ENABLE, VOP_HK_MASK); //default hsk mode bk background in HAL_MVOP_ResetReg()
3291 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3356 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3375 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/ |
| H A D | halMVOP.c | 1041 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1095 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1429 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_SetOutputTiming()
2902 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2909 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3149 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3203 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3263 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3316 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3374 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/ |
| H A D | halMVOP.c | 1003 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1057 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1335 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_SetOutputTiming()
2694 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2701 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2942 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
2985 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3043 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3085 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_DC2MVD_FLD_SEL); in HAL_MVOP_ResetReg()
3138 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/ |
| H A D | halMVOP.c | 1039 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1129 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2808 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2815 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3170 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3289 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3366 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3399 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
4373 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4407 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/ |
| H A D | halMVOP.c | 1024 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1118 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2791 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2798 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3153 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3271 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3348 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3381 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
4361 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4395 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/ |
| H A D | halMVOP.c | 1041 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1131 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2810 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2817 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3173 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3293 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3370 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3403 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
4405 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4439 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/ |
| H A D | halMVOP.c | 1026 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1080 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2844 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2851 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3091 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3196 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3298 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3339 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3790 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_EnableHDRSetting()
4382 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/ |
| H A D | halMVOP.c | 1005 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1059 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2803 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2810 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3048 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3146 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3242 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3280 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3666 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_EnableHDRSetting()
4178 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| H A D | regMVOP.h | 311 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/ |
| H A D | halMVOP.c | 1024 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1078 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2822 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2829 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
3068 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3169 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3268 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3309 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3760 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_EnableHDRSetting()
4323 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| H A D | regMVOP.h | 314 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/ |
| H A D | halMVOP.c | 951 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1002 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2574 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2581 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2814 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
2884 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3203 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3221 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3958 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4007 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/ |
| H A D | halMVOP.c | 983 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1034 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2701 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2708 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2942 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3033 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3118 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3151 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3965 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4012 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| H A D | regMVOP.h | 307 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/ |
| H A D | halMVOP.c | 1016 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1068 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2748 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2755 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2995 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3083 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3169 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3224 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
4379 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4426 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| H A D | regMVOP.h | 308 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/ |
| H A D | halMVOP.c | 1016 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
1068 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2748 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2755 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2995 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3083 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3169 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
3224 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background in HAL_MVOP_SetHandShakeMode()
4384 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
4431 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| H A D | regMVOP.h | 308 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/mustang/mvop/ |
| H A D | halMVOP.c | 909 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
960 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2507 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2514 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3); in HAL_MVOP_SetRptPreVsyncFrame()
2747 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
2817 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
3474 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
3523 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD); in HAL_MVOP_SubSetInputMode()
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| H A D | regMVOP.h | 309 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/maldives/mvop/ |
| H A D | halMVOP.c | 827 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
866 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD); in HAL_MVOP_SetInputMode()
2088 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD); in HAL_MVOP_ResetReg()
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| H A D | regMVOP.h | 291 #define VOP_MIRROR_CFG_HI (MVOP_REG_BASE + 0x77) macro
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