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Searched refs:TSP_SEM_ORDER (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c345 #define TSP_SEM_ORDER (_virtRegBase+ 0xC1484UL) // TSP_HW_SEMAPHORE1, TS3 0x21 macro
352 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
364 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
366 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
378 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
380 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
455 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c349 #define TSP_SEM_ORDER (_virtRegBase+ 0xC1484UL) // TSP_HW_SEMAPHORE1, TS3 0x21 macro
356 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
368 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
370 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
382 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
384 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
459 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c346 #define TSP_SEM_ORDER (_virtRegBase+ 0xC1484UL) // TSP_HW_SEMAPHORE1, TS3 0x21 macro
353 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
365 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
367 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
379 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
381 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
456 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c423 #define TSP_SEM_ORDER (_u32RegBase+ 0xC1484) // sw_mail_box1 macro
430 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
442 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
444 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
456 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
458 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
533 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c541 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
548 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
560 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
562 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
574 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
576 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
651 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c555 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
562 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
574 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
576 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
588 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
590 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
665 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c492 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
499 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
511 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
513 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
525 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
527 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
602 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c561 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
568 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
580 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
582 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
594 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
596 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
671 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c561 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
568 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
580 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
582 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
594 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
596 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
671 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c579 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
586 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
598 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
600 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
612 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
614 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
689 #undef TSP_SEM_ORDER
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c579 #define TSP_SEM_ORDER (_virtRegBase+ 0x2b58UL) // sw_mail_box1 macro
586 REG16_T(TSP_SEM_ORDER) = 0; in HAL_TSP_HW_Lock_Init()
598 REG16_T(TSP_SEM_ORDER) = 0xFFFF; in _HAL_TSP_HW_TryLock()
600 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()
612 REG16_T(TSP_SEM_ORDER) = 0x00; in _HAL_TSP_HW_TryLock()
614 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()
689 #undef TSP_SEM_ORDER