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Searched refs:TIMER_1_CTRL_REG (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/wdt/drv/wdt/
H A DdrvWDT.c688 HAL_WDT_WriteByte(TIMER_1_CTRL_REG,TIMER_DISABLE); in _MDrv_TIMER_Trigger()
689 HAL_WDT_WriteByte(TIMER_1_CTRL_REG,HAL_WDT_ReadByte(TIMER_1_CTRL_REG)|TIMER_TRIGGER); in _MDrv_TIMER_Trigger()
704 HAL_WDT_WriteByte(TIMER_1_CTRL_REG,HAL_WDT_ReadByte(TIMER_1_CTRL_REG)&(~TIMER_ENABLE)); in MDrv_TIMER_Stop()
733 HAL_WDT_WriteByte(TIMER_1_CTRL_REG,HAL_WDT_ReadByte(TIMER_1_CTRL_REG)|TIMER_ENABLE); in MDrv_TIMER_Count_U2K()
735 HAL_WDT_WriteByte(TIMER_1_CTRL_REG,HAL_WDT_ReadByte(TIMER_1_CTRL_REG)&(~TIMER_ENABLE)); in MDrv_TIMER_Count_U2K()
774 HAL_WDT_WriteByte(TIMER_1_CTRL_REG+1,HAL_WDT_ReadByte(TIMER_1_CTRL_REG+1)|TIMER_INTEN); in MDrv_TIMER_INT_U2K()
776 HAL_WDT_WriteByte(TIMER_1_CTRL_REG+1,HAL_WDT_ReadByte(TIMER_1_CTRL_REG+1)&(~TIMER_INTEN)); in MDrv_TIMER_INT_U2K()
842 HAL_WDT_WriteByte(TIMER_1_CTRL_REG,HAL_WDT_ReadByte(TIMER_1_CTRL_REG)|TIMER_ENABLE); in MDrv_TIMER_Rst_U2K()
/utopia/UTPA2-700.0.x/modules/wdt/hal/kano/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/manhattan/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7821/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maxim/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mainz/wdt/
H A DregWDT.h111 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maserati/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/curry/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6lite/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/messi/wdt/
H A DregWDT.h111 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maldives/wdt/
H A DregWDT.h111 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mustang/wdt/
H A DregWDT.h111 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mooney/wdt/
H A DregWDT.h111 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7621/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/macan/wdt/
H A DregWDT.h134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) macro