Searched refs:TIMER_0_CTRL_REG (Results 1 – 16 of 16) sorted by relevance
682 HAL_WDT_WriteByte(TIMER_0_CTRL_REG,TIMER_DISABLE); in _MDrv_TIMER_Trigger()683 HAL_WDT_WriteByte(TIMER_0_CTRL_REG,HAL_WDT_ReadByte(TIMER_0_CTRL_REG)|TIMER_TRIGGER); in _MDrv_TIMER_Trigger()699 HAL_WDT_WriteByte(TIMER_0_CTRL_REG,HAL_WDT_ReadByte(TIMER_0_CTRL_REG)&(~TIMER_ENABLE)); in MDrv_TIMER_Stop()726 HAL_WDT_WriteByte(TIMER_0_CTRL_REG,HAL_WDT_ReadByte(TIMER_0_CTRL_REG)|TIMER_ENABLE); in MDrv_TIMER_Count_U2K()728 HAL_WDT_WriteByte(TIMER_0_CTRL_REG,HAL_WDT_ReadByte(TIMER_0_CTRL_REG)&(~TIMER_ENABLE)); in MDrv_TIMER_Count_U2K()767 HAL_WDT_WriteByte(TIMER_0_CTRL_REG+1,HAL_WDT_ReadByte(TIMER_0_CTRL_REG+1)|TIMER_INTEN); in MDrv_TIMER_INT_U2K()769 HAL_WDT_WriteByte(TIMER_0_CTRL_REG+1,HAL_WDT_ReadByte(TIMER_0_CTRL_REG+1)&(~TIMER_INTEN)); in MDrv_TIMER_INT_U2K()840 HAL_WDT_WriteByte(TIMER_0_CTRL_REG,HAL_WDT_ReadByte(TIMER_0_CTRL_REG)|TIMER_ENABLE); in MDrv_TIMER_Rst_U2K()
129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL) macro
106 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00) macro