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Searched refs:T8_RIU_BASE (Results 1 – 25 of 38) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mfe/hal/curry/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x1; // 4'b0001, disable MFE clock in MHal_MFE_PowerOff()
251 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x0; break; // 4'b0000 in MHal_MFE_PowerOff()
253 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x4; break; // 4'b0100 in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x8; break; // 4'b1000 in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100 in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100 in MHal_MFE_PowerOff()
271 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) |= (1UL << 20); in MHal_MFE_PowerOff()
274 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) &= ~(1UL << 20); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
167 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7621/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
261 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
263 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
275 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) |= ((MS_U16)1); in MHal_MFE_PowerOff()
278 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) &= ~((MS_U16)1); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/maxim/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
261 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
263 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
275 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) |= ((MS_U16)1); in MHal_MFE_PowerOff()
278 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) &= ~((MS_U16)1); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/kano/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x1; // 4'b0001, disable MFE clock in MHal_MFE_PowerOff()
251 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x0; break; // 4'b0000 in MHal_MFE_PowerOff()
253 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x4; break; // 4'b0100 in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x8; break; // 4'b1000 in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100 in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100 in MHal_MFE_PowerOff()
271 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) |= (1UL << 20); in MHal_MFE_PowerOff()
274 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) &= ~(1UL << 20); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
167 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7821/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
261 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
263 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
275 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) |= ((MS_U16)1); in MHal_MFE_PowerOff()
278 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) &= ~((MS_U16)1); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/maserati/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
261 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
263 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
275 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) |= ((MS_U16)1); in MHal_MFE_PowerOff()
278 *((volatile MS_U16 *)(MS_VIRT)(T8_RIU_BASE + 0x11100*2 + 0x50*2*2)) &= ~((MS_U16)1); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/k6/mfe_ex/
H A Dmhal_mfe.c245 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x1; // 4'b0001, disable MFE clock in MHal_MFE_PowerOff()
251 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x0; break; // 4'b0000 in MHal_MFE_PowerOff()
253 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x4; break; // 4'b0100 in MHal_MFE_PowerOff()
255 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0x8; break; // 4'b1000 in MHal_MFE_PowerOff()
257 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100 in MHal_MFE_PowerOff()
259 *(MS_U16*)(T8_RIU_BASE + (REG_CKG_MFE * 4)) = 0xC; break; // 4'b1100 in MHal_MFE_PowerOff()
271 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) |= (1UL << 20); in MHal_MFE_PowerOff()
274 *((volatile MS_U32 *)(MS_VIRT)(T8_RIU_BASE + 0x71200*2 + 0x10*2*2)) &= ~(1UL << 20); in MHal_MFE_PowerOff()
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
167 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/maldives/mfe_ex/
H A Dmhal_mfe.h133 #define T8_RIU_BASE u32MFERegOSBase // = 0x25000000; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MFE_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE u32MFERegOSBase // = 0xBF200000; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80 // = 0xBF200000; //CH4 macro
H A Dmhal_mfe.c218 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
227 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
229 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
231 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
233 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
235 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
/utopia/UTPA2-700.0.x/modules/mfe/hal/mustang/mfe_ex/
H A Dmhal_mfe.h133 #define T8_RIU_BASE u32MFERegOSBase // = 0x25000000; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MFE_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE u32MFERegOSBase // = 0xBF200000; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80 // = 0xBF200000; //CH4 macro
H A Dmhal_mfe.c218 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
227 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
229 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
231 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
233 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
235 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
/utopia/UTPA2-700.0.x/modules/mfe/hal/mainz/mfe_ex/
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
152 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
154 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
156 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
H A Dmhal_mfe.c218 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
227 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
229 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
231 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
233 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
235 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
/utopia/UTPA2-700.0.x/modules/mfe/hal/macan/mfe_ex/
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
/utopia/UTPA2-700.0.x/modules/mfe/hal/manhattan/mfe_ex/
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
156 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
158 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
160 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
H A Dmhal_mfe.c218 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
227 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
229 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
231 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
233 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
235 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
/utopia/UTPA2-700.0.x/modules/mfe/hal/messi/mfe_ex/
H A Dmhal_mfe.h133 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0x25000000UL; G2 RIU base. macro
135 #define __MFE_REG(reg) (*(volatile MS_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
150 #define T8_RIU_BASE ((MS_VIRT)u32MFERegOSBase) // = 0xBF200000UL; //CH4 macro
152 #define __MFE_REG(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
154 #define __MFE_REG1(reg) (*(volatile MS_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
156 #define T8_RIU_BASE 0x0a80UL // = 0xBF200000UL; //CH4 macro
H A Dmhal_mfe.c218 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock in MHal_MFE_PowerOff()
227 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break; in MHal_MFE_PowerOff()
229 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break; in MHal_MFE_PowerOff()
231 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break; in MHal_MFE_PowerOff()
233 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()
235 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break; in MHal_MFE_PowerOff()

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