xref: /utopia/UTPA2-700.0.x/modules/mfe/hal/maldives/mfe_ex/mhal_mfe.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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#ifndef _MHAL_MFE_H_
#define _MHAL_MFE_H_

#if defined(_MFE_UTOPIA_)
#include <stdio.h>
#endif

#include "MFE_chip.h"
#include "drv_mfe_st.h"
#if defined(_MIPS_PLATFORM_)
#if defined(_MFE_BIG2_)
#include <sys/bsdtypes.h>
#include "shellcfg.h"   //for diag_printf
#elif defined(_KERNEL_MODE_)&&defined(_MFE_T8_)
#include "mdrv_types.h"
#elif defined(__MOBILE_CASE__)
#include "msutil/MsTypes.h"
#else
#include "MsTypes.h"
#endif
#endif

#include "mfe_type.h"
#include "mfe_common.h"

#ifdef _MFE_BIG2_
#define MIU_SHIFT     2//3
#define MIU_SIZE     4//8
#else
#define MIU_SHIFT     3
#define MIU_SIZE     8
#endif

#if defined(_AEON_PLATFORM_) && defined(_MFE_T8_)
	extern U32 RIU_BASE;// = 0xA0000000;
	#define REG_BANK_MFE    0x111000
	#define __MFE_REG(reg)		(*(volatile U16 *) ( RIU_BASE + (REG_BANK_MFE + reg*2)*2) )
#elif defined(__MFE_G2__)
	#define T8_RIU_BASE u32MFERegOSBase // = 0x25000000; G2 RIU base.
	#define REG_BANK_MFE  0x400
	#define __MFE_REG(reg) (*(volatile MFE_U32 *) (void*)( T8_RIU_BASE + (reg)*4 ) )
#elif defined(_AEON_PLATFORM_)
	extern U32 RIU_BASE;// = 0xA0000000;
	#define REG_BANK_MFE    0x1200
	#define __MFE_REG(reg)		(*(volatile U16 *) ( RIU_BASE + (REG_BANK_MFE + reg)*4) )
//extern U8 FSwrite_ready;
#elif defined(_MFE_BIG2_) && defined(_MIPS_PLATFORM_)
	extern U32 RIU_BASE;// = 0xBF834000;
	#define REG_BANK_MFE    0
	#define __MFE_REG(reg)        (*(volatile U16 *) ( RIU_BASE + REG_BANK_MFE + (reg)*4) )
#elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
	extern MFE_U32 RIU_BASE;// = 0xBF200000; //CH4
	#define REG_BANK_MFE    0x8800
	#define __MFE_REG(reg)		(*(volatile MFE_U16 *) ( RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
#elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& defined(_MFE_UTOPIA_)
	#define T8_RIU_BASE u32MFERegOSBase // = 0xBF200000; //CH4
#ifdef _MFE_KAISER_
	#define REG_BANK_MFE    0x11380
#else
    #define REG_BANK_MFE    0x8800
#endif
	#define __MFE_REG(reg)		(*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE + reg) * 4 ) )
    #define REG_BANK_MFE1    0x8880
    #define __MFE_REG1(reg)		(*(volatile MFE_U16 *) ( T8_RIU_BASE + (REG_BANK_MFE1 + reg) * 4 ) )
#else //if defined(_WIN32)//defined(_BCB_PLATFORM_)
    #define T8_RIU_BASE 0x0a80 // = 0xBF200000; //CH4
	#define REG_BANK_MFE 0x0a80 //Local FPGA
	#define REG_BANK_MFE1 0x0b80 //Local FPGA
    //#define T8_RIU_BASE 0x0b80 // = 0xBF200000; //CH4
	//#define REG_BANK_MFE 0x0b80 //Local FPGA
	//#define REG_BANK_MFE1 0x01080 //Local FPGA
#endif

MS_BOOL MHal_MFE_GetHWCap(MS_U16 *width, MS_U16 *height);

#if (defined(_MFE_T8_)||defined(_MFE_M1_)) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_)
void MHAL_MFE_InitRegBase(MFE_U32 u32RegBase);
void MHAL_MFE_CreateRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1);
void MHAL_MFE_DelRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1);
#endif
void MHal_MFE_PowerOff(MFE_U32 is_off,MFE_CLK_LEVEL clock_level);
MFE_U32 MHal_MFE_GetBitstreamEncodedLen(void);
void MHal_MFE_set_outbitsbuf(MFE_REG* mfe_reg, OutBitSBUF *bitsbuf,int outbufsize);
void MHal_MFE_SetIrqMask(MFE_U16 mask);

#ifdef MFE_MIU_PROTECT
void MHal_MFE_Enable_MIU_Protection(int MIU_TEST_MODE,MFE_CONFIG* pConfig);
void MHal_MFE_Enable_MIU_Protection_Check(int MIU_TEST_MODE,int TYPE);
#endif
MFE_U32 MHal_MFE_CycleReport(void);
void MHal_MFE_ClearIRQ(MFE_U16 irq_bits);
void MHal_MFE_GetIRQ(MFE_U16 *irq_bits);
void MHal_MFE_SWReset(MFE_REG* mfe_reg);
void MHal_MFE_start(void);
void MHal_MFE_SetCLKCTL(MFE_REG* mfe_reg);
void MHal_MFE_ResetReg(MFE_REG* mfe_reg);
void MHal_MFE_GetCRC(MFE_U8 checksum_HW[8]);
#endif//_MHAL_MFE_H_