Searched refs:RIUBASE_IRQ_HYP (Results 1 – 11 of 11) sorted by relevance
112 #define RIUBASE_IRQ_HYP 0x1000 //(0x101000-0x100000) macro125 #define REG_AEON_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x24 << 1)) //NOT EXIST NOW126 #define REG_AEON_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + (0x2C << 1)) //NOT EXIST NOW127 #define REG_AEON_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x2C << 1)) //NOT EXIST NOW131 #define REG_AEON_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x34 << 1)) //NOT EXIST NOW132 #define REG_AEON_C_IRQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x3C << 1)) //NOT EXIST NOW145 #define REG_MIPS_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x44 << 1))146 #define REG_MIPS_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + (0x4C << 1))147 #define REG_MIPS_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x4C << 1))151 #define REG_MIPS_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x54 << 1))[all …]
108 #define RIUBASE_IRQ_HYP 0x1000 //(0x101000-0x100000) macro158 #define REG_AEON_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x64*2)) //NOT EXIST NOW159 #define REG_AEON_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + (0x6C*2)) //NOT EXIST NOW160 #define REG_AEON_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x6C*2)) //NOT EXIST NOW165 #define REG_AEON_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x74*2)) //NOT EXIST NOW166 #define REG_AEON_C_IRQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x7C*2)) //NOT EXIST NOW185 #define REG_MIPS_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + 0x24*2)186 #define REG_MIPS_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + 0x2C*2)187 #define REG_MIPS_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + 0x2C*2)192 #define REG_MIPS_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + 0x34*2)[all …]
108 #define RIUBASE_IRQ_HYP 0x1000 //(0x101000-0x100000) macro158 #define REG_AEON_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x64*2)) //NOT EXIST NOW159 #define REG_AEON_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + (0x6C*2)) //NOT EXIST NOW160 #define REG_AEON_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x6C*2)) //NOT EXIST NOW165 #define REG_AEON_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + (0x74*2)) //NOT EXIST NOW166 #define REG_AEON_C_IRQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + (0x7C*2)) //NOT EXIST NOW185 #define REG_MIPS_C_FIQ_HYP_MASK (RIUBASE_IRQ_HYP + 0x24*2) //[IRQ][HAL][011] Mask b…186 #define REG_MIPS_C_FIQ_HYP_CLR (RIUBASE_IRQ_HYP + 0x2C*2) //[IRQ][HAL][012] Clear …187 #define REG_MIPS_C_FIQ_HYP_FINAL_STATUS (RIUBASE_IRQ_HYP + 0x2C*2) //[IRQ][HAL][013] Status…192 #define REG_MIPS_C_IRQ_HYP_MASK (RIUBASE_IRQ_HYP + 0x34*2) //[IRQ][HAL][014] Mask b…[all …]